Andrew Waterman
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56c4f44c2a
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hellacache returns!
but AMOs are unimplemented.
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2011-12-12 06:49:39 -08:00 |
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Andrew Waterman
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ce201559f3
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Support cache->cpu nacks one cycle after request
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2011-12-10 00:42:09 -08:00 |
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Andrew Waterman
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c01e1f1cef
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Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
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2011-12-09 19:42:58 -08:00 |
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Rimas Avizienis
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e70b41241c
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changed branch addr generation to get it off critical path
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2011-12-02 01:56:17 -08:00 |
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Rimas Avizienis
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da2fdf4f85
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fixed console i/o
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2011-11-30 22:51:59 -08:00 |
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Rimas Avizienis
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bc44572d99
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bugfixes due to new hcl jar file
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2011-11-30 21:54:55 -08:00 |
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Rimas Avizienis
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11f0e3daf4
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more cleanup
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2011-11-18 00:17:30 -08:00 |
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Rimas Avizienis
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c42d8149b7
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moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl
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2011-11-17 23:50:45 -08:00 |
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Rimas Avizienis
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80b4253318
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fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
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2011-11-16 02:04:28 -08:00 |
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Rimas Avizienis
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886857fa47
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writes of PC weren't being sign extended
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2011-11-15 18:07:36 -08:00 |
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Rimas Avizienis
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48cec01710
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updated riscv-bmarks and riscv-tests to build with new toolchain
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2011-11-15 00:11:22 -08:00 |
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Rimas Avizienis
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cd6e463320
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added ei and di instructions
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2011-11-14 13:48:49 -08:00 |
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Rimas Avizienis
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b791010bb1
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flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
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2011-11-14 04:13:13 -08:00 |
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Rimas Avizienis
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890bfa7c48
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added IPIs and timer interrupts
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2011-11-14 03:24:02 -08:00 |
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Rimas Avizienis
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5b29765917
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synced up with supervisor mode state in latest ISA simulator
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2011-11-14 01:37:20 -08:00 |
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Rimas Avizienis
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44419511b7
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timer interrupt fixes
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2011-11-13 00:32:08 -08:00 |
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Rimas Avizienis
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f86d5b1334
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cleanup, lots of minor fixes, added more PCR regs (COREID, NUMCORES), parameterized BTB
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2011-11-10 11:26:13 -08:00 |
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Rimas Avizienis
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4bd0263a4a
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added misaligned instruction check, cleaned up badvaddr handling
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2011-11-10 03:38:59 -08:00 |
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Rimas Avizienis
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603ede8bfe
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access faults now write badvaddr PCR register with faulting address
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2011-11-10 02:46:09 -08:00 |
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Rimas Avizienis
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36aa4bcc9d
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moved exception handling from ex stage in dpath to mem stage in ctrl
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2011-11-10 02:26:26 -08:00 |
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Rimas Avizienis
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62407b4668
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more tlb/ptw fixes
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2011-11-10 00:23:29 -08:00 |
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Rimas Avizienis
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6664af3bc0
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cleanup before adding dtlb
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2011-11-09 23:27:29 -08:00 |
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Rimas Avizienis
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9aca403aa8
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more itlb integration & cleanup
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2011-11-09 23:18:14 -08:00 |
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Rimas Avizienis
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c29d2821b4
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cleanup, fixes, initial commit for dtlb.scala
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2011-11-09 21:54:11 -08:00 |
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Rimas Avizienis
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e96430d862
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integrating ITLB & PTW
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2011-11-09 14:52:17 -08:00 |
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Rimas Avizienis
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7130edac8d
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fix for flushed div/mul instructions
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2011-11-07 01:03:47 -08:00 |
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Rimas Avizienis
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4d64099103
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cleanup
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2011-11-04 20:52:21 -07:00 |
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Rimas Avizienis
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4459935554
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dcache fixes - all tests and ubmarks pass, hello world still broken
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2011-11-04 15:40:41 -07:00 |
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Rimas Avizienis
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3a02028a35
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fixes to exception and dcache miss/blocked handling
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2011-11-02 13:32:32 -07:00 |
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Rimas Avizienis
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7a528d6255
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fixes for div/mul hazard checking + cleanup
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2011-11-01 23:14:34 -07:00 |
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Rimas Avizienis
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d8ffecf565
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dcache fix
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2011-11-01 22:10:06 -07:00 |
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Rimas Avizienis
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7479e085ec
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 22:04:45 -07:00 |
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Rimas Avizienis
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3b3d988fde
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dcache loads working - 1/2 cycle load/use delay depending on load type
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2011-11-01 21:25:52 -07:00 |
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Rimas Avizienis
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2b67eee683
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pipeline changes for replay on dcache miss
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2011-11-01 19:05:27 -07:00 |
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Rimas Avizienis
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08b89e7710
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interface cleanup, major pipeline changes
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2011-11-01 17:59:27 -07:00 |
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Rimas Avizienis
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c06e2d16e4
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initial commit of rocket chisel project, riscv assembly tests and benchmarks
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2011-10-25 23:02:47 -07:00 |
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