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massive refactoring of vector constants

This commit is contained in:
Yunsup Lee 2012-02-25 15:55:10 -08:00
parent 3980120279
commit 3839e3a318
3 changed files with 8 additions and 8 deletions
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2
rocket/src/main/scala/dpath.scala
View File

@ -41,7 +41,7 @@ class ioDpathAll extends Bundle()
val vec_ctrl = new ioCtrlDpathVec().flip()
val vec_iface = new ioDpathVecInterface()
val vec_imul_req = new io_imul_req
val vec_imul_resp = Bits(hwacha.Config.DEF_XLEN, INPUT)
val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT)
}
class rocketDpath extends Component

8
rocket/src/main/scala/dpath_vec.scala
View File

@ -4,13 +4,13 @@ import Chisel._
import Node._
import Constants._
import Instructions._
import hwacha.Interface._
import hwacha.Constants._
class ioDpathVecInterface extends Bundle
{
val vcmdq_bits = Bits(VCMD_SZ, OUTPUT)
val vximm1q_bits = Bits(VIMM_SZ, OUTPUT)
val vximm2q_bits = Bits(VSTRIDE_SZ, OUTPUT)
val vcmdq_bits = Bits(SZ_VCMD, OUTPUT)
val vximm1q_bits = Bits(SZ_VIMM, OUTPUT)
val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
}
class ioDpathVec extends Bundle

6
rocket/src/main/scala/multiplier.scala
View File

@ -4,7 +4,7 @@ import Chisel._
import Node._
import Constants._
import hwacha._
import hwacha.Config._
import hwacha.Constants._
class ioMultiplier extends Bundle {
val req = new io_imul_req().flip()
@ -13,7 +13,7 @@ class ioMultiplier extends Bundle {
val resp_val = Bool(OUTPUT)
val resp_rdy = Bool(INPUT)
val resp_tag = Bits(5, OUTPUT)
val resp_bits = Bits(DEF_XLEN, OUTPUT)
val resp_bits = Bits(SZ_XLEN, OUTPUT)
}
class rocketVUMultiplier(nwbq: Int) extends Component {
@ -21,7 +21,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component {
val cpu = new ioMultiplier
val vu = new Bundle {
val req = new io_imul_req
val resp = Bits(DEF_XLEN, INPUT)
val resp = Bits(SZ_XLEN, INPUT)
}
}