massive refactoring of vector constants
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3980120279
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3839e3a318
@ -41,7 +41,7 @@ class ioDpathAll extends Bundle()
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val vec_ctrl = new ioCtrlDpathVec().flip()
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val vec_iface = new ioDpathVecInterface()
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val vec_imul_req = new io_imul_req
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val vec_imul_resp = Bits(hwacha.Config.DEF_XLEN, INPUT)
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val vec_imul_resp = Bits(hwacha.Constants.SZ_XLEN, INPUT)
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}
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class rocketDpath extends Component
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@ -4,13 +4,13 @@ import Chisel._
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import Node._
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import Constants._
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import Instructions._
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import hwacha.Interface._
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import hwacha.Constants._
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class ioDpathVecInterface extends Bundle
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{
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val vcmdq_bits = Bits(VCMD_SZ, OUTPUT)
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val vximm1q_bits = Bits(VIMM_SZ, OUTPUT)
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val vximm2q_bits = Bits(VSTRIDE_SZ, OUTPUT)
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val vcmdq_bits = Bits(SZ_VCMD, OUTPUT)
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val vximm1q_bits = Bits(SZ_VIMM, OUTPUT)
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val vximm2q_bits = Bits(SZ_VSTRIDE, OUTPUT)
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}
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class ioDpathVec extends Bundle
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@ -4,7 +4,7 @@ import Chisel._
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import Node._
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import Constants._
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import hwacha._
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import hwacha.Config._
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import hwacha.Constants._
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class ioMultiplier extends Bundle {
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val req = new io_imul_req().flip()
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@ -13,7 +13,7 @@ class ioMultiplier extends Bundle {
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val resp_val = Bool(OUTPUT)
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val resp_rdy = Bool(INPUT)
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val resp_tag = Bits(5, OUTPUT)
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val resp_bits = Bits(DEF_XLEN, OUTPUT)
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val resp_bits = Bits(SZ_XLEN, OUTPUT)
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}
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class rocketVUMultiplier(nwbq: Int) extends Component {
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@ -21,7 +21,7 @@ class rocketVUMultiplier(nwbq: Int) extends Component {
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val cpu = new ioMultiplier
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val vu = new Bundle {
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val req = new io_imul_req
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val resp = Bits(DEF_XLEN, INPUT)
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val resp = Bits(SZ_XLEN, INPUT)
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}
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}
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