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@ -0,0 +1,850 @@
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package Top {
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import Chisel._
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import Node._;
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import Constants._;
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import scala.math._;
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class rocketNBDCacheStoreGen extends Component {
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val io = new Bundle {
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val req_type = Bits(3, 'input)
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val req_addr_lsb = Bits(3, 'input)
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val req_data = Bits(64, 'input)
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val store_wmask = Bits(8, 'output)
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val store_data = Bits(64, 'output)
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}
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// generate write mask and store data signals based on store type and address LSBs
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val wmask = Wire { Bits(8) }
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switch (io.req_type(1,0))
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{
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is (MT_B) { wmask <== Bits( 1,1) << io.req_addr_lsb(2,0).toUFix }
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is (MT_H) { wmask <== Bits( 3,2) << Cat(io.req_addr_lsb(2,1), Bits(0,1)).toUFix }
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is (MT_W) { wmask <== Bits( 15,4) << Cat(io.req_addr_lsb(2,2), Bits(0,2)).toUFix }
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otherwise { wmask <== Bits(255,8) } // MT_D
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}
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val data = Wire { Bits(64) }
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switch (io.req_type(1,0))
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{
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is (MT_B) { data <== Fill(8, io.req_data( 7,0)) }
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is (MT_H) { data <== Fill(4, io.req_data(15,0)) }
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is (MT_W) { data <== Fill(2, io.req_data(31,0)) }
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otherwise { data <== io.req_data } // MT_D
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}
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io.store_wmask := wmask
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io.store_data := data
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}
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class DataMemCmd extends Bundle {
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val offset = Bits(width = OFFSET_BITS)
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val cmd = Bits(width = 4)
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val typ = Bits(width = 3)
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}
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class RPQEntry extends Bundle {
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val cmd = new DataMemCmd()
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val sdq_id = UFix(width = ceil(log(NSDQ)/log(2)).toInt)
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}
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class Replay extends Bundle {
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val idx = Bits(width = IDX_BITS)
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val cmd = new DataMemCmd()
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val sdq_id = UFix(width = ceil(log(NSDQ)/log(2)).toInt)
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}
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class DataReq extends Bundle {
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val idx = Bits(width = IDX_BITS)
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val cmd = new DataMemCmd()
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val data = Bits(width = CPU_DATA_BITS)
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}
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class DataArrayReq extends Bundle {
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val idx = Bits(width = IDX_BITS)
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val offset = Bits(width = ceil(log(REFILL_CYCLES)/log(2)).toInt)
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val rw = Bool()
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val wmask = Bits(width = MEM_DATA_BITS/8)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class MemReq extends Bundle {
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val rw = Bool()
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val addr = Bits(width = PPN_BITS+IDX_BITS)
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}
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class WritebackReq extends Bundle {
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val ppn = Bits(width = PPN_BITS)
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val idx = Bits(width = IDX_BITS)
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}
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class MetaData extends Bundle {
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val valid = Bool()
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val dirty = Bool()
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val tag = Bits(width = PPN_BITS)
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}
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class MetaReq extends Bundle {
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val idx = Bits(width = IDX_BITS)
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val rw = Bool()
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val data = new MetaData()
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}
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class MSHR extends Component {
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val io = new Bundle {
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val req_pri_val = Bool('input)
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val req_pri_rdy = Bool('output)
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val req_sec_val = Bool('input)
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val req_sec_rdy = Bool('output)
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val req_ppn = Bits(PPN_BITS, 'input)
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val req_idx = Bits(IDX_BITS, 'input)
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val req_cmd = new RPQEntry().asInput
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val req_tag = Bits(CPU_TAG_BITS, 'input)
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val idx_match = Bool('output)
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val tag = Bits(PPN_BITS, 'output)
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val mem_resp_val = Bool('input)
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val mem_req = (new ioDecoupled) { new MemReq() }.flip
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val meta_req = (new ioDecoupled) { new MetaReq() }.flip
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val replay = (new ioDecoupled) { new Replay() }.flip
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}
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val valid = Reg(resetVal = Bool(false))
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val dirty = Reg { Bool() }
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val requested = Reg { Bool() }
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val refilled = Reg { Bool() }
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val ppn = Reg { Bits() }
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val idx = Reg { Bits() }
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val req_load = (io.req_cmd.cmd.cmd === M_XRD) || (io.req_cmd.cmd.cmd === M_PRD) || (io.req_cmd.cmd.cmd === M_PFR)
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val req_use_rpq = (io.req_cmd.cmd.cmd != M_PFR) && (io.req_cmd.cmd.cmd != M_PFW)
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val next_dirty = io.req_pri_val && io.req_pri_rdy && !req_load || io.req_sec_val && io.req_sec_rdy && (!req_load || dirty)
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val sec_rdy = io.idx_match && !refilled && (dirty || !requested || req_load)
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val rpq = (new queueSimplePF(NRPQ)) { new RPQEntry() }
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rpq.io.q_reset := Bool(false)
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rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && req_use_rpq
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io.req_cmd ^^ rpq.io.enq.bits
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rpq.io.deq.ready := io.replay.ready && refilled
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when (io.req_pri_val && io.req_pri_rdy) {
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valid <== Bool(true)
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requested <== Bool(false)
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refilled <== Bool(false)
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ppn <== io.req_ppn
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idx <== io.req_idx
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}
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when (io.mem_req.valid && io.mem_req.ready) {
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requested <== Bool(true)
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}
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when (io.mem_resp_val) {
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refilled <== Bool(true)
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}
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when (io.meta_req.valid && io.meta_req.ready) {
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valid <== Bool(false)
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}
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dirty <== next_dirty
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io.idx_match := valid && (idx === io.req_idx)
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io.tag := ppn
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io.req_pri_rdy := !valid
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io.req_sec_rdy := sec_rdy && rpq.io.enq.ready
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io.meta_req.valid := valid && refilled && !rpq.io.deq.valid
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io.meta_req.bits.rw := Bool(true)
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io.meta_req.bits.idx := idx
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io.meta_req.bits.data.valid := Bool(true)
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io.meta_req.bits.data.dirty := dirty
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io.meta_req.bits.data.tag := ppn
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io.mem_req.valid := valid && !requested
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//io.mem_req.bits.itm := next_dirty
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io.mem_req.bits.rw := Bool(false)
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io.mem_req.bits.addr := Cat(ppn, idx)
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io.replay.valid := rpq.io.deq.valid && refilled
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io.replay.bits.idx := idx
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rpq.io.deq.bits.cmd ^^ io.replay.bits.cmd
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io.replay.bits.sdq_id := rpq.io.deq.bits.sdq_id
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}
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class MSHRFile extends Component {
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val io = new Bundle {
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val req_val = Bool('input)
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val req_rdy = Bool('output)
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val req_cmd = (new DataMemCmd).asInput
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val req_ppn = Bits(PADDR_BITS, 'input)
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val req_idx = Bits(IDX_BITS, 'input)
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val req_data = Bits(64, 'input)
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val req_tag = Bits(CPU_TAG_BITS, 'input)
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val mem_resp_val = Bool('input)
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val mem_resp_tag = Bits(DMEM_TAG_BITS, 'input)
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val mem_req = (new ioDecoupled) { new MemReq() }.flip()
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val meta_req = (new ioDecoupled) { new MetaReq() }.flip()
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val replay = (new ioDecoupled) { new Replay() }.flip()
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}
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val idx_match = Wire { Bool() }
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val pri_rdy = Wire { Bool() }
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val sec_rdy = Wire { Bool() }
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val tag_mux = new Mux1H(NMSHR, PPN_BITS)
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val meta_req_arb = (new Arbiter(NMSHR)) { new MetaReq() }
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val mem_req_arb = (new Arbiter(NMSHR)) { new MemReq() }
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val replay_arb = (new Arbiter(NMSHR)) { new RPQEntry() }
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val alloc_arb = (new Arbiter(NMSHR)) { Bool() }
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val tag_match = tag_mux.io.out === io.req_ppn
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for (i <- 0 to NMSHR-1) {
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val mshr = new MSHR()
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val rpqe = new RPQEntry().asInput
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rpqe.cmd.offset <== io.req_cmd.offset
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rpqe.cmd.cmd <== Mux(io.req_cmd.cmd === M_PRD, M_XRD, io.req_cmd.cmd)
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rpqe.cmd.typ <== io.req_cmd.typ
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rpqe.sdq_id <== UFix(0)
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tag_mux.io.sel(i) := mshr.io.idx_match
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tag_mux.io.in(i) := mshr.io.tag
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alloc_arb.io.in(i).valid := mshr.io.req_pri_rdy
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mshr.io.req_pri_val := io.req_val && !idx_match && alloc_arb.io.in(i).ready
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mshr.io.req_sec_val := io.req_val && tag_match
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mshr.io.req_ppn := io.req_ppn
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mshr.io.req_idx := io.req_idx
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mshr.io.req_tag := io.req_tag
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rpqe ^^ mshr.io.req_cmd
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mshr.io.meta_req <> meta_req_arb.io.in(i)
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mshr.io.mem_req <> mem_req_arb.io.in(i)
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mshr.io.replay <> replay_arb.io.in(i)
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mshr.io.mem_resp_val := io.mem_resp_val && (UFix(i) === io.mem_resp_tag)
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when (mshr.io.req_pri_rdy) { pri_rdy <== Bool(true) }
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when (mshr.io.req_sec_rdy) { sec_rdy <== Bool(true) }
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when (mshr.io.idx_match) { idx_match <== Bool(true) }
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}
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pri_rdy <== Bool(false)
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sec_rdy <== Bool(false)
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idx_match <== Bool(false)
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meta_req_arb.io.out ^^ io.meta_req
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mem_req_arb.io.out ^^ io.mem_req
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replay_arb.io.out ^^ io.replay
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io.req_rdy := Mux(idx_match, tag_match && sec_rdy, pri_rdy)
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}
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class StoreDataUnit extends Component {
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val io = new Bundle {
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val sdq_enq = (new ioDecoupled) { Bits(width = CPU_DATA_BITS) }
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val sdq_id = UFix(width = ceil(log(NSDQ)/log(2)).toInt, dir = 'output)
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val replay = (new ioDecoupled) { new Replay() }
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val data_req = (new ioDecoupled) { new DataReq() }.flip()
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}
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val cmdq = (new queueSimplePF(2)) { new Replay() }
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val dataq = (new queueSimplePF(2)) { Bits(width = CPU_DATA_BITS) }
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val next_dataq_enq_rdy = !dataq.io.deq.valid || dataq.io.enq.ready && (!dataq.io.enq.valid || dataq.io.deq.ready)
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val next_dataq_enq_val = io.replay.valid && next_dataq_enq_rdy && (io.replay.bits.cmd.cmd != M_XRD) && cmdq.io.enq.ready
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dataq.io.enq.valid := Reg(next_dataq_enq_val, resetVal = Bool(false))
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dataq.io.enq.bits := sdq_dout
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dataq.io.deq.ready := io.data_req.ready && (cmdq.io.deq.bits.cmd.cmd != M_XRD)
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cmdq.io.enq.valid := io.replay.valid && ((io.replay.bits.cmd.cmd === M_XRD) || next_dataq_enq_rdy)
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io.replay.bits ^^ cmdq.io.enq.bits
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cmdq.io.deq.ready := io.data_req.ready && ((cmdq.io.deq.bits.cmd.cmd === M_XRD) || dataq.io.deq.valid)
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val sdq = Mem4(NSDQ, io.sdq_enq.bits);
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sdq.setReadLatency(1);
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sdq.setTarget('inst);
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val sdq_addr = Mux(next_dataq_enq_val, io.replay.bits.sdq_id, io.sdq_id)
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val sdq_wen = io.sdq_enq.valid && io.sdq_enq.ready
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val sdq_dout = sdq.rw(sdq_addr, io.sdq_enq.bits, sdq_wen, cs = next_dataq_enq_val || sdq_wen);
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val sdq_val = Reg(resetVal = Bits(0, ceil(log(NSDQ)/log(2)).toInt))
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when (next_dataq_enq_val) { sdq_val <== sdq_val.bitSet(io.replay.bits.sdq_id, Bool(false)) }
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when (sdq_wen) { sdq_val <== sdq_val.bitSet(io.sdq_id, Bool(true)) }
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def priority_enc(in: Bits, n: Int = 0): Bits = if (in.width == n-1) UFix(n-1) else if(in(n) == Bool(true)) UFix(n) else priority_enc(in, n+1)
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io.sdq_id := priority_enc(~sdq_val)
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io.sdq_enq.ready := ((~sdq_val) != UFix(0)) && !next_dataq_enq_val
|
|
|
|
|
io.replay.ready := cmdq.io.enq.ready && next_dataq_enq_rdy
|
|
|
|
|
io.data_req.valid := cmdq.io.deq.valid && ((cmdq.io.deq.bits.cmd.cmd === M_XRD) || dataq.io.deq.valid)
|
|
|
|
|
io.data_req.bits.idx := cmdq.io.deq.bits.idx
|
|
|
|
|
cmdq.io.deq.bits.cmd ^^ io.data_req.bits.cmd
|
|
|
|
|
io.data_req.bits.data := dataq.io.deq.bits
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class WritebackUnit extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val wb_req = (new ioDecoupled) { new WritebackReq() }
|
|
|
|
|
val data_req = (new ioDecoupled) { new DataReq() }.flip()
|
|
|
|
|
val data_resp = Bits(width = MEM_DATA_BITS, dir = 'input)
|
|
|
|
|
val mem_req = (new ioDecoupled) { new MemReq() }.flip()
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val wbq = (new queueSimplePF(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) }
|
|
|
|
|
val valid = Reg(resetVal = Bool(false))
|
|
|
|
|
val cnt = Reg() { UFix(ceil(log(REFILL_CYCLES)/log(2)).toInt) }
|
|
|
|
|
val addr = Reg() { new WritebackReq() }
|
|
|
|
|
|
|
|
|
|
wbq.io.enq.valid := valid && Reg(io.data_req.valid && io.data_req.ready)
|
|
|
|
|
wbq.io.enq.bits := io.data_resp
|
|
|
|
|
wbq.io.deq.ready := io.mem_req.ready && (~cnt === UFix(0))
|
|
|
|
|
|
|
|
|
|
when (io.wb_req.valid && io.wb_req.ready) { valid <== Bool(true); cnt <== UFix(0); addr <== io.wb_req.bits }
|
|
|
|
|
when (io.data_req.valid && io.data_req.ready) { cnt <== cnt + UFix(1) }
|
|
|
|
|
when ((~cnt === UFix(0)) && !wbq.io.deq.valid) { valid <== Bool(false) }
|
|
|
|
|
|
|
|
|
|
io.wb_req.ready := !valid
|
|
|
|
|
io.data_req.valid := valid && wbq.io.enq.ready
|
|
|
|
|
io.data_req.bits.idx := addr.idx
|
|
|
|
|
io.data_req.bits.cmd.offset := cnt * UFix(MEM_DATA_BITS/8)
|
|
|
|
|
io.data_req.bits.cmd.cmd := M_XRD
|
|
|
|
|
io.data_req.bits.cmd.typ := UFix(0)
|
|
|
|
|
io.data_req.bits.data := wbq.io.deq.bits
|
|
|
|
|
io.mem_req.valid := wbq.io.deq.valid && (~cnt === UFix(0))
|
|
|
|
|
io.mem_req.bits.rw := Bool(true)
|
|
|
|
|
io.mem_req.bits.addr := Cat(addr.ppn, addr.idx)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class FlushUnit extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val flush_req = (new ioDecoupled) { Bits(width = CPU_TAG_BITS) }
|
|
|
|
|
val flush_resp = (new ioDecoupled) { Bits(width = CPU_TAG_BITS) }.flip()
|
|
|
|
|
val meta_req = (new ioDecoupled) { new MetaReq() }.flip()
|
|
|
|
|
val meta_resp = (new MetaData).asInput()
|
|
|
|
|
|
|
|
|
|
val wb_req_val = Bool(dir = 'output)
|
|
|
|
|
val wb_req_rdy = Bool(dir = 'input)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val s_reset :: s_ready :: s_meta_read :: s_meta_wait :: s_writeback :: s_meta_write :: s_done :: Nil = Enum(7) { UFix() }
|
|
|
|
|
val state = Reg(resetVal = s_reset)
|
|
|
|
|
val tag = Reg() { Bits(width = CPU_TAG_BITS) }
|
|
|
|
|
val cnt = Reg() { UFix(ceil(log(REFILL_CYCLES)/log(2)).toInt) }
|
|
|
|
|
val next_cnt = cnt + UFix(1)
|
|
|
|
|
|
|
|
|
|
switch (state) {
|
|
|
|
|
is(s_reset) { when (io.meta_req.ready) { state <== Mux(~cnt === UFix(0), s_ready, s_reset); cnt <== next_cnt } }
|
|
|
|
|
is(s_ready) { when (io.flush_req.valid) { state <== s_meta_read; tag <== io.flush_req.bits } }
|
|
|
|
|
is(s_meta_read) { when (io.meta_req.ready) { state <== s_meta_wait } }
|
|
|
|
|
is(s_meta_wait) { state <== Mux(io.meta_resp.valid && io.meta_resp.dirty, s_writeback, s_meta_write) }
|
|
|
|
|
is(s_writeback) { when (io.wb_req_rdy) { state <== s_meta_write } }
|
|
|
|
|
is(s_meta_write) { when (io.meta_req.ready) { state <== Mux(~cnt === UFix(0), s_done, s_meta_read); cnt <== next_cnt } }
|
|
|
|
|
is(s_done) { when (io.flush_resp.ready) { state <== s_ready } }
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
io.flush_req.ready := state === s_ready
|
|
|
|
|
io.flush_resp.valid := state === s_done
|
|
|
|
|
io.flush_resp.bits := tag
|
|
|
|
|
io.meta_req.valid := (state === s_meta_read) || (state === s_meta_write) || (state === s_reset)
|
|
|
|
|
io.meta_req.bits.idx := cnt
|
|
|
|
|
io.meta_req.bits.rw := (state === s_meta_write) || (state === s_reset)
|
|
|
|
|
io.meta_req.bits.data.valid := Bool(false)
|
|
|
|
|
io.meta_req.bits.data.dirty := Bool(false)
|
|
|
|
|
io.meta_req.bits.data.tag := UFix(0)
|
|
|
|
|
io.wb_req_val := state === s_writeback
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class MetaDataArray(lines: Int) extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val req = (new ioDecoupled) { new MetaReq() }
|
|
|
|
|
val resp = (new MetaData).asOutput()
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val array = Mem4(lines, io.resp)
|
|
|
|
|
array.setReadLatency(1)
|
|
|
|
|
array.setTarget('inst)
|
|
|
|
|
val rdata = array.rw(io.req.bits.idx, io.req.bits.data, io.req.valid && io.req.bits.rw, cs = io.req.valid)
|
|
|
|
|
rdata ^^ io.resp
|
|
|
|
|
io.req.ready := Bool(true)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class DataArray(lines: Int) extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val req = (new ioDecoupled) { new DataArrayReq() }
|
|
|
|
|
val resp = Bits(width = MEM_DATA_BITS, dir = 'output)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val wmask_array = Vec(MEM_DATA_BITS/8) { Wire() { Bits(width = MEM_DATA_BITS) } }
|
|
|
|
|
wmask_array(0) <== Fill(8, io.req.bits.wmask(0))
|
|
|
|
|
for (i <- 1 to MEM_DATA_BITS/8-1) {
|
|
|
|
|
wmask_array(i) <== Cat(Fill(8, io.req.bits.wmask(i)), wmask_array(i-1)(8*(i+1)-1, 8*i))
|
|
|
|
|
}
|
|
|
|
|
val wmask = wmask_array(MEM_DATA_BITS/8-1)
|
|
|
|
|
|
|
|
|
|
val array = Mem4(lines*REFILL_CYCLES, io.resp)
|
|
|
|
|
array.setReadLatency(1)
|
|
|
|
|
array.setTarget('inst)
|
|
|
|
|
val addr = Cat(io.req.bits.idx, io.req.bits.offset)
|
|
|
|
|
val rdata = array.rw(addr, io.req.bits.data, io.req.valid && io.req.bits.rw, wmask, cs = io.req.valid)
|
|
|
|
|
rdata ^^ io.resp
|
|
|
|
|
io.req.ready := Bool(true)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// state machine to flush (write back dirty lines, invalidate clean ones) the D$
|
|
|
|
|
class rocketNBDCacheDM_flush(lines: Int) extends Component {
|
|
|
|
|
val io = new ioDCacheDM();
|
|
|
|
|
val dcache = new rocketNBDCacheDM(lines);
|
|
|
|
|
|
|
|
|
|
val addrbits = PADDR_BITS;
|
|
|
|
|
val indexbits = ceil(log10(lines)/log10(2)).toInt;
|
|
|
|
|
val offsetbits = 6;
|
|
|
|
|
val tagmsb = addrbits - 1;
|
|
|
|
|
val taglsb = indexbits+offsetbits;
|
|
|
|
|
val tagbits = tagmsb-taglsb+1;
|
|
|
|
|
val indexmsb = taglsb-1;
|
|
|
|
|
val indexlsb = offsetbits;
|
|
|
|
|
val offsetmsb = indexlsb-1;
|
|
|
|
|
val offsetlsb = 3;
|
|
|
|
|
|
|
|
|
|
val flush_count = Reg(resetVal = UFix(0, indexbits));
|
|
|
|
|
val flush_resp_count = Reg(resetVal = UFix(0, indexbits));
|
|
|
|
|
val flushing = Reg(resetVal = Bool(false));
|
|
|
|
|
val flush_waiting = Reg(resetVal = Bool(false));
|
|
|
|
|
val r_cpu_req_tag = Reg(resetVal = Bits(0, 5));
|
|
|
|
|
|
|
|
|
|
when (io.cpu.req_val && io.cpu.req_rdy && (io.cpu.req_cmd === M_FLA))
|
|
|
|
|
{
|
|
|
|
|
r_cpu_req_tag <== io.cpu.req_tag;
|
|
|
|
|
flushing <== Bool(true);
|
|
|
|
|
flush_waiting <== Bool(true);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
when (dcache.io.cpu.req_rdy && (flush_count === ~Bits(0, indexbits))) {
|
|
|
|
|
flushing <== Bool(false);
|
|
|
|
|
}
|
|
|
|
|
when (dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag === r_cpu_req_tag) && (flush_resp_count === ~Bits(0, indexbits))) {
|
|
|
|
|
flush_waiting <== Bool(false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
when (flushing && dcache.io.cpu.req_rdy) {
|
|
|
|
|
flush_count <== flush_count + UFix(1,1);
|
|
|
|
|
}
|
|
|
|
|
when (flush_waiting && dcache.io.cpu.resp_val && (dcache.io.cpu.resp_tag(5,0) === r_cpu_req_tag)) {
|
|
|
|
|
flush_resp_count <== flush_resp_count + UFix(1,1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
dcache.io.cpu.req_val := (io.cpu.req_val && (io.cpu.req_cmd != M_FLA) && !flush_waiting) || flushing;
|
|
|
|
|
dcache.io.cpu.req_cmd := Mux(flushing, M_FLA, io.cpu.req_cmd);
|
|
|
|
|
dcache.io.cpu.req_idx := Mux(flushing, Cat(flush_count, Bits(0,offsetbits)), io.cpu.req_idx);
|
|
|
|
|
dcache.io.cpu.req_ppn := Mux(flushing, UFix(0,PPN_BITS), io.cpu.req_ppn);
|
|
|
|
|
dcache.io.cpu.req_tag := Mux(flushing, r_cpu_req_tag, io.cpu.req_tag);
|
|
|
|
|
dcache.io.cpu.req_type := io.cpu.req_type;
|
|
|
|
|
dcache.io.cpu.req_data ^^ io.cpu.req_data;
|
|
|
|
|
dcache.io.cpu.dtlb_miss := io.cpu.dtlb_miss;
|
|
|
|
|
dcache.io.mem ^^ io.mem;
|
|
|
|
|
|
|
|
|
|
io.cpu.xcpt_ma_ld := dcache.io.cpu.xcpt_ma_ld;
|
|
|
|
|
io.cpu.xcpt_ma_st := dcache.io.cpu.xcpt_ma_st;
|
|
|
|
|
io.cpu.req_rdy := dcache.io.cpu.req_rdy && !flush_waiting;
|
|
|
|
|
io.cpu.resp_miss := dcache.io.cpu.resp_miss;
|
|
|
|
|
io.cpu.resp_data := dcache.io.cpu.resp_data;
|
|
|
|
|
io.cpu.resp_tag := dcache.io.cpu.resp_tag;
|
|
|
|
|
io.cpu.resp_val := dcache.io.cpu.resp_val &
|
|
|
|
|
!(flush_waiting && (io.cpu.resp_tag === r_cpu_req_tag) && (flush_count != ~Bits(0, addrbits)));
|
|
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
class rocketNBDCacheAMOALU extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val cmd = Bits(4, 'input)
|
|
|
|
|
val wmask = Bits(64/8, 'input)
|
|
|
|
|
val lhs = UFix(64, 'input)
|
|
|
|
|
val rhs = UFix(64, 'input)
|
|
|
|
|
val result = UFix(64, 'output)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val signed = (io.cmd === M_XA_MIN) || (io.cmd === M_XA_MAX)
|
|
|
|
|
val sub = (io.cmd === M_XA_MIN) || (io.cmd === M_XA_MINU) || (io.cmd === M_XA_MAX) || (io.cmd === M_XA_MAXU)
|
|
|
|
|
val min = (io.cmd === M_XA_MIN) || (io.cmd === M_XA_MINU)
|
|
|
|
|
|
|
|
|
|
val addsub_rhs = Mux(sub, ~io.rhs, io.rhs)
|
|
|
|
|
val adder_lhs = Cat(io.lhs(63,32), io.wmask(3) & io.lhs(31), io.lhs(30,0)).toUFix;
|
|
|
|
|
val adder_rhs = Cat(addsub_rhs(63,32), io.wmask(3) & addsub_rhs(31), addsub_rhs(30,0)).toUFix;
|
|
|
|
|
val adder_out = adder_lhs + adder_rhs + sub.toUFix
|
|
|
|
|
|
|
|
|
|
val cmp_lhs = Mux(io.wmask(7), io.lhs(63), io.lhs(31))
|
|
|
|
|
val cmp_rhs = Mux(io.wmask(7), io.rhs(63), io.rhs(31))
|
|
|
|
|
val cmp_diff = Mux(io.wmask(7), adder_out(63), adder_out(31))
|
|
|
|
|
val less = Mux(cmp_lhs === cmp_rhs, cmp_diff, Mux(signed, cmp_lhs, cmp_rhs))
|
|
|
|
|
val cmp_out = Mux(min === less, io.lhs, io.rhs)
|
|
|
|
|
|
|
|
|
|
val alu_out = Wire() { UFix() };
|
|
|
|
|
switch (io.cmd) {
|
|
|
|
|
is (M_XA_ADD) { alu_out <== adder_out }
|
|
|
|
|
is (M_XA_SWAP) { alu_out <== io.rhs }
|
|
|
|
|
is (M_XA_AND) { alu_out <== io.lhs & io.rhs }
|
|
|
|
|
is (M_XA_OR) { alu_out <== io.lhs | io.rhs }
|
|
|
|
|
}
|
|
|
|
|
alu_out <== cmp_out
|
|
|
|
|
|
|
|
|
|
io.result := alu_out
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
// XXX broken for CPU_DATA_WIDTH != 64
|
|
|
|
|
class AMOUnit extends Component {
|
|
|
|
|
val io = new Bundle {
|
|
|
|
|
val req = (new ioDecoupled) { new DataReq() }
|
|
|
|
|
val lhs = Bits(width = CPU_DATA_BITS)
|
|
|
|
|
val rhs = Bits(width = CPU_DATA_BITS)
|
|
|
|
|
val wmask = Bits(width = CPU_DATA_BITS/8, dir = 'input)
|
|
|
|
|
val data_req = (new ioDecoupled) { new DataReq() }.flip()
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val valid = Reg(resetVal = Bool(false))
|
|
|
|
|
val r_cmd = Reg() { new DataMemCmd() }
|
|
|
|
|
val r_idx = Reg() { Bits(width = IDX_BITS) }
|
|
|
|
|
val r_lhs = Reg() { Bits(width = 64) }
|
|
|
|
|
val r_rhs = Reg() { Bits(width = 64) }
|
|
|
|
|
val r_wmask = Reg() { Bits(width = 64/8) }
|
|
|
|
|
when (io.req.valid && io.req.ready) {
|
|
|
|
|
valid <== Bool(true);
|
|
|
|
|
r_idx <== io.req.bits.idx
|
|
|
|
|
r_lhs <== io.lhs;
|
|
|
|
|
r_rhs <== io.rhs;
|
|
|
|
|
r_cmd <== io.req.bits.cmd;
|
|
|
|
|
r_wmask <== io.wmask
|
|
|
|
|
}
|
|
|
|
|
when (io.data_req.valid && io.data_req.ready) {
|
|
|
|
|
valid <== Bool(false)
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
val alu = new rocketNBDCacheAMOALU
|
|
|
|
|
alu.io.cmd := r_cmd.cmd
|
|
|
|
|
alu.io.wmask := r_wmask
|
|
|
|
|
alu.io.lhs := r_lhs
|
|
|
|
|
alu.io.rhs := r_rhs
|
|
|
|
|
|
|
|
|
|
io.req.ready := !valid
|
|
|
|
|
io.data_req.valid := valid
|
|
|
|
|
io.data_req.bits.idx := r_idx
|
|
|
|
|
r_cmd ^^ io.data_req.bits.cmd
|
|
|
|
|
io.data_req.bits.data := alu.io.result
|
|
|
|
|
}
|
|
|
|
|
|
|
|
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class rocketNBDCacheDM(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log(lines)/log(2)).toInt;
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val offsetbits = OFFSET_BITS;
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val tagmsb = PADDR_BITS-1;
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val taglsb = indexbits+offsetbits;
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val tagbits = tagmsb-taglsb+1;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = ceil(log(CPU_DATA_BITS/8)/log(2)).toInt;
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val s_reset :: s_ready :: s_replay_load :: s_write_amo :: s_start_writeback :: s_writeback :: s_req_refill :: s_refill :: s_resolve_miss :: Nil = Enum(9) { UFix() };
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val state = Reg(resetVal = s_reset);
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// idx arrives one clock cycle prior to ppn b/c of DTLB
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val r_cpu_req_idx = Reg(resetVal = Bits(0, PGIDX_BITS));
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val r_cpu_req_ppn = Reg(resetVal = Bits(0, PPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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val r_cpu_req_cmd = Reg(resetVal = Bits(0,4));
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val r_cpu_req_type = Reg(resetVal = Bits(0,3));
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val r_cpu_req_tag = Reg(resetVal = Bits(0,5));
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val r_cpu_resp_val = Reg(resetVal = Bool(false));
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val r_amo_data = Reg(resetVal = Bits(0,64));
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val p_store_data = Reg(resetVal = Bits(0,64));
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val p_store_idx = Reg(resetVal = Bits(0,PGIDX_BITS));
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val p_store_type = Reg(resetVal = Bits(0,3));
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val p_store_valid = Reg(resetVal = Bool(false));
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val req_store = (io.cpu.req_cmd === M_XWR);
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val req_load = (io.cpu.req_cmd === M_XRD) || (io.cpu.req_cmd === M_PRD);
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val req_flush = (io.cpu.req_cmd === M_FLA);
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val req_amo = io.cpu.req_cmd(3).toBool;
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val r_req_load = (r_cpu_req_cmd === M_XRD) || (r_cpu_req_cmd === M_PRD);
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val r_req_store = (r_cpu_req_cmd === M_XWR);
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val r_req_flush = (r_cpu_req_cmd === M_FLA);
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val r_req_ptw_load = (r_cpu_req_cmd === M_PRD);
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val r_req_amo = r_cpu_req_cmd(3).toBool;
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_idx <== io.cpu.req_idx;
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r_cpu_req_cmd <== io.cpu.req_cmd;
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r_cpu_req_type <== io.cpu.req_type;
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r_cpu_req_tag <== io.cpu.req_tag;
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}
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when ((state === s_ready) && r_cpu_req_val && !io.cpu.dtlb_miss) {
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r_cpu_req_ppn <== io.cpu.req_ppn;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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when (((state === s_resolve_miss) && (r_req_load || r_req_amo)) || (state === s_replay_load)) {
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r_cpu_resp_val <== Bool(true);
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}
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otherwise {
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r_cpu_resp_val <== Bool(false);
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}
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// refill counter
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val rr_count = Reg(resetVal = UFix(0,2));
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val rr_count_next = rr_count + UFix(1);
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when (((state === s_refill) && io.mem.resp_val) || ((state === s_writeback) && io.mem.req_rdy)) {
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rr_count <== rr_count_next;
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}
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// tag array
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val tag_addr =
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Mux((state === s_ready), io.cpu.req_idx(PGIDX_BITS-1,offsetbits),
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r_cpu_req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we =
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((state === s_refill) && io.mem.resp_val && (rr_count === UFix(3,2))) ||
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((state === s_resolve_miss) && r_req_flush);
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val tag_array = Mem4(lines, r_cpu_req_ppn);
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tag_array.setReadLatency(SRAM_READ_LATENCY);
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// tag_array.setTarget('inst);
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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when (tag_we && !r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we && r_req_flush) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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val vb_rdata = vb_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;
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val tag_valid = r_cpu_req_val && vb_rdata;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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val tag_hit = tag_valid && tag_match;
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val miss = r_cpu_req_val && (!vb_rdata || !tag_match);
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// load/store addresses conflict if they are to any part of the same 64 bit word
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val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetlsb) === p_store_idx(PGIDX_BITS-1,offsetlsb));
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val ldst_conflict = tag_valid && tag_match && (r_req_load || r_req_amo) && p_store_valid && addr_match;
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val store_hit = r_cpu_req_val && !io.cpu.dtlb_miss && tag_hit && r_req_store ;
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// write the pending store data when the cache is idle, when the next command isn't a load
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// or when there's a load to the same address (in which case there's a 2 cycle delay:
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// once cycle to write the store data and another to read the data back)
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val drain_store =
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((store_hit || p_store_valid) && (!io.cpu.req_val || req_store || req_flush)) ||
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(p_store_valid && (miss || ldst_conflict));
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// write pending store data from a store which missed
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// after the cache line refill has completed
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val resolve_store = (state === s_resolve_miss) && r_req_store;
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// pending store data
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when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
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p_store_idx <== io.cpu.req_idx;
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p_store_data <== io.cpu.req_data;
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p_store_type <== io.cpu.req_type;
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}
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when (store_hit && !drain_store) {
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p_store_valid <== Bool(true);
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}
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when (drain_store) {
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p_store_valid <== Bool(false);
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}
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// AMO operand
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when (io.cpu.req_val && io.cpu.req_rdy && req_amo) {
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r_amo_data <== io.cpu.req_data;
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}
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// dirty bit array
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val db_array = Reg(resetVal = Bits(0, lines));
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val tag_dirty = db_array(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix).toBool;
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when ((r_cpu_req_val && !io.cpu.dtlb_miss && tag_hit && r_req_store) || resolve_store) {
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db_array <== db_array.bitSet(p_store_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (state === s_write_amo) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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when (tag_we) {
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db_array <== db_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(0,1));
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}
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val mshr = new MSHRFile()
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mshr.io.req_val := r_cpu_req_val
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mshr.io.req_ppn := r_cpu_req_ppn
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mshr.io.req_idx := r_cpu_req_idx(PGIDX_BITS-1, offsetbits)
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mshr.io.req_cmd.offset := r_cpu_req_idx(offsetbits-1, 0)
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mshr.io.req_cmd.cmd := r_cpu_req_cmd
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mshr.io.req_cmd.typ := r_cpu_req_type
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// generate write mask and data signals for stores and amos
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val storegen = new rocketDCacheStoreGen();
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storegen.io.req_addr_lsb := p_store_idx(2,0);
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storegen.io.req_data := p_store_data;
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storegen.io.req_type := p_store_type;
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val store_data = Fill(2, storegen.io.store_data);
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val store_wmask_d = storegen.io.store_wmask;
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val store_wmask = Mux(p_store_idx(offsetlsb).toBool, Cat(store_wmask_d, Bits(0,64)), Cat(Bits(0,64), store_wmask_d));
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// ALU for AMOs
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val amo_alu = new rocketNBDCacheAMOALU();
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val amo_alu_out = Cat(amo_alu.io.result,amo_alu.io.result);
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val amo_wmask =
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Mux(r_cpu_req_type === MT_D, ~Bits(0,8),
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Mux(r_cpu_req_idx(2).toBool, Cat(~Bits(0,4), Bits(0,4)),
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Cat(Bits(0,4), ~Bits(0,4))));
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val amo_store_wmask_d = Cat(Fill(8, amo_wmask(7)),
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Fill(8, amo_wmask(6)),
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Fill(8, amo_wmask(5)),
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Fill(8, amo_wmask(4)),
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Fill(8, amo_wmask(3)),
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Fill(8, amo_wmask(2)),
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Fill(8, amo_wmask(1)),
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Fill(8, amo_wmask(0)));
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val amo_store_wmask = Mux(r_cpu_req_idx(offsetlsb).toBool, Cat(amo_store_wmask_d, Bits(0,64)), Cat(Bits(0,64), amo_store_wmask_d));
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// data array
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val data_addr =
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Mux(drain_store || resolve_store, p_store_idx(PGIDX_BITS-1, offsetmsb-1),
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Mux((state === s_writeback) && io.mem.req_rdy, Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count_next),
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Mux((state === s_start_writeback) || (state === s_writeback) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
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Mux((state === s_resolve_miss) || (state === s_replay_load) || (state === s_write_amo), r_cpu_req_idx(PGIDX_BITS-1, offsetmsb-1),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1))))).toUFix;
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val data_wdata =
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Mux((state === s_refill), io.mem.resp_data,
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Mux((state === s_write_amo), amo_alu_out,
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store_data));
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val data_we =
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((state === s_refill) && io.mem.resp_val) ||
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(state === s_write_amo) ||
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drain_store || resolve_store;
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val data_wmask =
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Mux((state === s_refill), ~Bits(0,128),
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Mux((state === s_write_amo), amo_store_wmask,
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store_wmask));
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val data_array = Mem4(lines*4, data_wdata);
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data_array.setReadLatency(SRAM_READ_LATENCY);
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// data_array.setTarget('inst);
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val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
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val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
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val r_resp_data = Reg(resp_data);
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amo_alu.io.cmd := r_cpu_req_cmd;
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amo_alu.io.wmask := amo_wmask;
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amo_alu.io.lhs := Mux(r_cpu_resp_val, resp_data, r_resp_data).toUFix;
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amo_alu.io.rhs := r_amo_data.toUFix;
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// signal a load miss when the data isn't present in the cache and when it's in the pending store data register
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// (causes the cache to block for 2 cycles and the load or amo instruction is replayed)
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val load_miss =
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!io.cpu.dtlb_miss &&
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(state === s_ready) && r_cpu_req_val && (r_req_load || r_req_amo) && (!tag_hit || (p_store_valid && addr_match));
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// output signals
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// busy when there's a load to the same address as a pending store, or on a cache miss, or when executing a flush
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io.cpu.req_rdy := mshr.io.req_rdy && (state === s_ready) && !io.cpu.dtlb_miss && !ldst_conflict && (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo)));
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io.cpu.resp_val := !io.cpu.dtlb_miss &&
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((state === s_ready) && tag_hit && (r_req_load || r_req_amo) && !(p_store_valid && addr_match)) ||
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((state === s_resolve_miss) && r_req_flush) ||
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r_cpu_resp_val;
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val misaligned =
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(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
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(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val && (r_req_load || r_req_amo) && misaligned;
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io.cpu.xcpt_ma_st := r_cpu_req_val && (r_req_store || r_req_amo) && misaligned;
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io.cpu.resp_miss := load_miss;
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// tag MSB distinguishes between loads destined for the PTW and CPU
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io.cpu.resp_tag := Cat(r_req_ptw_load, r_cpu_req_type, r_cpu_req_idx(2,0), r_cpu_req_tag);
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io.cpu.resp_data := resp_data;
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io.mem.req_val := (state === s_req_refill) || (state === s_writeback);
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io.mem.req_rw := (state === s_writeback);
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io.mem.req_wdata := data_array_rdata;
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io.mem.req_tag := UFix(0);
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io.mem.req_addr :=
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Mux(state === s_writeback, Cat(tag_rdata, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), rr_count),
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Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2))).toUFix;
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// control state machine
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switch (state) {
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is (s_reset) {
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state <== s_ready;
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}
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is (s_ready) {
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when (io.cpu.dtlb_miss) {
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state <== s_ready;
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}
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when (ldst_conflict) {
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state <== s_replay_load;
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}
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when (!r_cpu_req_val || (tag_hit && !(r_req_flush || r_req_amo))) {
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state <== s_ready;
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}
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when (tag_hit && r_req_amo) {
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state <== s_write_amo;
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}
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when (tag_valid & tag_dirty) {
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state <== s_start_writeback;
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}
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when (r_req_flush) {
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state <== s_resolve_miss;
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}
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otherwise {
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state <== s_req_refill;
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}
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}
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is (s_replay_load) {
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state <== s_ready;
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}
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is (s_write_amo) {
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|
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state <== s_ready;
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}
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is (s_start_writeback) {
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|
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state <== s_writeback;
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}
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is (s_writeback) {
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when (io.mem.req_rdy && (rr_count === UFix(3,2))) {
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|
|
when (r_req_flush) {
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|
|
state <== s_resolve_miss;
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|
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}
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|
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otherwise {
|
|
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|
|
state <== s_req_refill;
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|
|
|
|
}
|
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|
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}
|
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|
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}
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|
|
is (s_req_refill)
|
|
|
|
|
{
|
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|
|
when (io.mem.req_rdy) { state <== s_refill; }
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|
|
}
|
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|
|
is (s_refill) {
|
|
|
|
|
when (io.mem.resp_val && (rr_count === UFix(3,2))) { state <== s_resolve_miss; }
|
|
|
|
|
}
|
|
|
|
|
is (s_resolve_miss) {
|
|
|
|
|
when (r_req_amo) {
|
|
|
|
|
state <== s_write_amo;
|
|
|
|
|
}
|
|
|
|
|
state <== s_ready;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
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|
|
|
}
|
Andrew Waterman