access faults now write badvaddr PCR register with faulting address
This commit is contained in:
parent
36aa4bcc9d
commit
603ede8bfe
@ -33,11 +33,14 @@ class ioCtrlDpath extends Bundle()
|
||||
val sel_wb = UFix(3, 'output);
|
||||
val ren_pcr = Bool('output);
|
||||
val wen_pcr = Bool('output);
|
||||
val exception = Bool('output);
|
||||
val cause = UFix(5,'output);
|
||||
val eret = Bool('output);
|
||||
val mem_load = Bool('output);
|
||||
val wen = Bool('output);
|
||||
// exception handling
|
||||
val exception = Bool('output);
|
||||
val cause = UFix(5,'output);
|
||||
val badvaddr_wen = Bool('output); // high for any access fault
|
||||
val badvaddr_sel = Bool('output); // select between instruction PC or load/store addr
|
||||
// inputs from datapath
|
||||
val btb_hit = Bool('input);
|
||||
val inst = Bits(32, 'input);
|
||||
@ -389,7 +392,9 @@ class rocketCtrl extends Component
|
||||
// write cause to PCR on an exception
|
||||
io.dpath.exception := mem_exception;
|
||||
io.dpath.cause := mem_cause;
|
||||
|
||||
io.dpath.badvaddr_wen := io.xcpt_dtlb_ld || io.xcpt_dtlb_st || mem_reg_xcpt_itlb;
|
||||
io.dpath.badvaddr_sel := mem_reg_xcpt_itlb;
|
||||
|
||||
// replay execute stage PC when the D$ is blocked, when the D$ misses, and for privileged instructions
|
||||
val replay_ex = (ex_reg_mem_val && !io.dmem.req_rdy) || io.dmem.resp_miss || mem_reg_privileged;
|
||||
|
||||
|
@ -108,6 +108,7 @@ class rocketDpath extends Component
|
||||
// writeback definitions
|
||||
val wb_reg_valid = Reg(resetVal = Bool(false));
|
||||
val wb_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS));
|
||||
val wb_reg_mem_req_addr = Reg(resetVal = UFix(0,VADDR_BITS));
|
||||
val wb_reg_waddr = Reg(resetVal = UFix(0,5));
|
||||
val wb_reg_wdata = Reg(resetVal = Bits(0,64));
|
||||
val wb_reg_ctrl_ll_wb = Reg(resetVal = Bool(false));
|
||||
@ -117,6 +118,8 @@ class rocketDpath extends Component
|
||||
val wb_reg_ctrl_exception = Reg(resetVal = Bool(false));
|
||||
val wb_reg_ctrl_wen = Reg(resetVal = Bool(false));
|
||||
val wb_reg_ctrl_wen_pcr = Reg(resetVal = Bool(false));
|
||||
val wb_reg_badvaddr_sel = Reg(resetVal = Bool(false));
|
||||
val wb_reg_badvaddr_wen = Reg(resetVal = Bool(false));
|
||||
|
||||
val r_dmem_resp_val = Reg(resetVal = Bool(false));
|
||||
val r_dmem_resp_waddr = Reg(resetVal = UFix(0,5));
|
||||
@ -412,6 +415,9 @@ class rocketDpath extends Component
|
||||
wb_reg_ctrl_eret <== mem_reg_ctrl_eret;
|
||||
wb_reg_ctrl_exception <== io.ctrl.exception;
|
||||
wb_reg_ctrl_cause <== io.ctrl.cause;
|
||||
wb_reg_mem_req_addr <== io.dmem.req_addr;
|
||||
wb_reg_badvaddr_wen <== io.ctrl.badvaddr_wen;
|
||||
wb_reg_badvaddr_sel <== io.ctrl.badvaddr_sel;
|
||||
|
||||
when (io.ctrl.killm) {
|
||||
wb_reg_valid <== Bool(false);
|
||||
@ -448,10 +454,13 @@ class rocketDpath extends Component
|
||||
pcr.io.w.en := wb_reg_ctrl_wen_pcr;
|
||||
pcr.io.w.data := wb_reg_wdata;
|
||||
|
||||
pcr.io.eret := wb_reg_ctrl_eret;
|
||||
pcr.io.exception := wb_reg_ctrl_exception;
|
||||
pcr.io.cause := wb_reg_ctrl_cause;
|
||||
pcr.io.pc := wb_reg_pc;
|
||||
pcr.io.eret := wb_reg_ctrl_eret;
|
||||
pcr.io.exception := wb_reg_ctrl_exception;
|
||||
pcr.io.cause := wb_reg_ctrl_cause;
|
||||
pcr.io.pc := wb_reg_pc;
|
||||
pcr.io.ldst_addr := wb_reg_mem_req_addr;
|
||||
pcr.io.badvaddr_wen := wb_reg_badvaddr_wen;
|
||||
pcr.io.badvaddr_sel := wb_reg_badvaddr_sel;
|
||||
|
||||
// temporary debug outputs so things don't get optimized away
|
||||
io.debug.id_valid := id_reg_valid;
|
||||
|
@ -40,7 +40,10 @@ class ioDpathPCR extends Bundle()
|
||||
val evec = UFix(VADDR_BITS, 'output);
|
||||
val exception = Bool('input);
|
||||
val cause = UFix(5, 'input);
|
||||
val badvaddr_wen = Bool('input);
|
||||
val badvaddr_sel = Bool('input);
|
||||
val pc = UFix(VADDR_BITS, 'input);
|
||||
val ldst_addr = UFix(VADDR_BITS, 'input);
|
||||
val eret = Bool('input);
|
||||
}
|
||||
|
||||
@ -95,6 +98,10 @@ class rocketDpathPCR extends Component
|
||||
}
|
||||
}
|
||||
|
||||
when (io.badvaddr_wen) {
|
||||
reg_badvaddr <== Mux(io.badvaddr_sel, io.pc, io.ldst_addr);
|
||||
}
|
||||
|
||||
when (io.exception && !reg_status_et) {
|
||||
reg_error_mode <== Bool(true);
|
||||
}
|
||||
@ -106,7 +113,7 @@ class rocketDpathPCR extends Component
|
||||
reg_epc <== io.pc;
|
||||
reg_cause <== io.cause;
|
||||
}
|
||||
|
||||
|
||||
when (!io.exception && io.eret) {
|
||||
reg_status_s <== reg_status_ps;
|
||||
reg_status_et <== Bool(true);
|
||||
|
Loading…
Reference in New Issue
Block a user