upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache

rocket/src/main/scala/cpu.scala

@@ -191,27 +191,32 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
     vu.io.cpu_exception.exception := dpath.io.vec_iface.exception
 
     // hooking up vector memory interface
-    //arb.io.requestor(2) <> vu.io.dmem_req
-    /*ctrl.io.ext_mem.req_val := vu.io.dmem_req.valid
-    ctrl.io.ext_mem.req_cmd := vu.io.dmem_req.bits.cmd
-    ctrl.io.ext_mem.req_type := vu.io.dmem_req.bits.typ
+    val storegen = new StoreDataGen
+    storegen.io.typ := vu.io.dmem_req.bits.typ
+    storegen.io.din := vu.io.dmem_req.bits.data
 
-    dpath.io.ext_mem.req_val := vu.io.dmem_req.valid
-    dpath.io.ext_mem.req_idx := vu.io.dmem_req.bits.idx
-    dpath.io.ext_mem.req_ppn := vu.io.dmem_req.bits.ppn
-    dpath.io.ext_mem.req_data := vu.io.dmem_req.bits.data
-    dpath.io.ext_mem.req_tag := vu.io.dmem_req.bits.tag
+    arb.io.requestor(2).req_val := vu.io.dmem_req.valid
+    arb.io.requestor(2).req_kill := Reg(vu.io.dmem_req.bits.kill)
+    arb.io.requestor(2).req_cmd := vu.io.dmem_req.bits.cmd
+    arb.io.requestor(2).req_type := vu.io.dmem_req.bits.typ
+    arb.io.requestor(2).req_idx := vu.io.dmem_req.bits.idx
+    arb.io.requestor(2).req_ppn := Reg(vu.io.dmem_req.bits.ppn)
+    arb.io.requestor(2).req_data := Reg(storegen.io.dout)
+    arb.io.requestor(2).req_tag := vu.io.dmem_req.bits.tag
 
-    vu.io.dmem_resp.valid := dpath.io.ext_mem.resp_val
-    vu.io.dmem_resp.bits.nack := ctrl.io.ext_mem.resp_nack
-    vu.io.dmem_resp.bits.data := dpath.io.ext_mem.resp_data
-    vu.io.dmem_resp.bits.tag := dpath.io.ext_mem.resp_tag
-    vu.io.dmem_resp.bits.typ := dpath.io.ext_mem.resp_type*/
+    vu.io.dmem_resp.valid := Reg(arb.io.requestor(2).resp_val)
+    // the vu doesn't look at the ready signal, it's simply a nack
+    // but should be delayed one cycle to match the nack semantics
+    vu.io.dmem_resp.bits.nack := arb.io.requestor(2).resp_nack || Reg(!arb.io.requestor(2).req_rdy)
+    vu.io.dmem_resp.bits.data := arb.io.requestor(2).resp_data_subword
+    vu.io.dmem_resp.bits.tag := Reg(arb.io.requestor(2).resp_tag)
+    vu.io.dmem_resp.bits.typ := Reg(arb.io.requestor(2).resp_type)
 
     // share vector integer multiplier with rocket
     dpath.io.vec_imul_req <> vu.io.cp_imul_req
     dpath.io.vec_imul_resp <> vu.io.cp_imul_resp
 
+    // share sfma and dfma pipelines with rocket
     fpu.io.sfma <> vu.io.cp_sfma
     fpu.io.dfma <> vu.io.cp_dfma
   }

rocket/src/main/scala/dpath.scala

@@ -19,7 +19,7 @@ class ioDpathAll extends Bundle()
   val ctrl  = new ioCtrlDpath().flip();
   val debug = new ioDebug();
   val dmem  = new ioDmem(List("req_idx", "req_tag", "req_data", "resp_val", "resp_miss", "resp_replay", "resp_type", "resp_tag", "resp_data", "resp_data_subword")).flip();
-  val dtlb = new ioDTLB_CPU_req_bundle(List("vpn"))
+  val dtlb = new ioDTLB_CPU_req_bundle().asOutput()
   val imem  = new ioDpathImem();
   val ptbr_wen = Bool(OUTPUT);
   val ptbr = UFix(PADDR_BITS, OUTPUT);

rocket/src/main/scala/dtlb.scala

@@ -9,7 +9,7 @@ import hwacha._
 // ioDTLB_CPU also located in hwacha/src/vuVXU-Interface.scala
 // should keep them in sync
 
-class ioDTLB_CPU_req_bundle(view: List[String] = null) extends Bundle(view)
+class ioDTLB_CPU_req_bundle extends Bundle
 {
   // lookup requests
   val kill  = Bool()

rocket/src/main/scala/nbdcache.scala

@@ -954,7 +954,7 @@ class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
   amoalu.io.lhs := loadgen.io.r_dout.toUFix
   amoalu.io.rhs := p_store_data.toUFix
 
-  early_nack := early_tag_nack || early_load_nack || r_cpu_req_val_ && r_req_amo || replay_amo_val || r_replay_amo
+  early_nack := early_tag_nack || early_load_nack || r_cpu_req_val && r_req_amo || replay_amo_val || r_replay_amo
 
   // reset and flush unit
   val flusher = new FlushUnit(lines)

rocket/src/main/scala/ptw.scala

@@ -55,8 +55,10 @@ class rocketDmemArbiter(n: Int) extends Component
   for (i <- 0 until n)
   {
     val tag_hit = io.dmem.resp_tag(log2up(n)-1,0) === UFix(i)
-    io.requestor(i).resp_miss := io.dmem.resp_miss && tag_hit
+    io.requestor(i).xcpt_ma_ld := io.dmem.xcpt_ma_ld && Reg(io.requestor(i).req_val)
+    io.requestor(i).xcpt_ma_st := io.dmem.xcpt_ma_st && Reg(io.requestor(i).req_val)
     io.requestor(i).resp_nack := io.dmem.resp_nack && Reg(io.requestor(i).req_val)
+    io.requestor(i).resp_miss := io.dmem.resp_miss && tag_hit
     io.requestor(i).resp_val := io.dmem.resp_val && tag_hit
     io.requestor(i).resp_replay := io.dmem.resp_replay && tag_hit
     io.requestor(i).resp_data := io.dmem.resp_data