more itlb integration & cleanup
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c29d2821b4
commit
9aca403aa8
@ -9,7 +9,7 @@ class ioMem() extends Bundle
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val req_val = Bool('output);
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val req_rdy = Bool('input);
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val req_rw = Bool('output);
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val req_addr = UFix(32, 'output);
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val req_addr = UFix(PADDR_BITS, 'output);
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val req_wdata = Bits(128, 'output);
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val req_tag = Bits(4, 'output);
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@ -67,7 +67,7 @@ class rocketMemArbiter extends Component {
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io.dcache.resp_data := io.mem.resp_data;
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io.icache.resp_tag := io.mem.resp_tag(2,0);
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io.dcache.resp_tag := io.mem.resp_tag(2,0);
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// io.dcache.resp_tag := io.mem.resp_tag(2,0);
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}
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@ -29,7 +29,7 @@ class ioDcache(view: List[String] = null) extends Bundle(view) {
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val req_wdata = Bits(128, 'input);
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val req_rw = Bool('input);
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val resp_data = Bits(128, 'output);
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val resp_tag = Bits(3, 'output);
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// val resp_tag = Bits(3, 'output);
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val resp_val = Bool('output);
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}
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@ -49,7 +49,7 @@ class rocketDpath extends Component
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val rfile = new rocketDpathRegfile();
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// instruction fetch definitions
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val if_reg_pc = Reg(width = 32, resetVal = UFix(0, 32));
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val if_reg_pc = Reg(resetVal = UFix(0,VADDR_BITS));
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// instruction decode definitions
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val id_reg_valid = Reg(resetVal = Bool(false));
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@ -128,8 +128,8 @@ class rocketDpath extends Component
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Cat(Fill(52, ex_reg_inst(31)), ex_reg_inst(31,27), ex_reg_inst(16,10));
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val branch_adder_rhs =
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Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(30,0), UFix(0, 1)),
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Cat(Fill(6, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
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Mux(io.ctrl.sel_pc === PC_BR, Cat(ex_sign_extend_split(41,0), UFix(0, 1)),
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Cat(Fill(17, ex_reg_inst(31)), ex_reg_inst(31,7), UFix(0, 1)));
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val ex_branch_target = ex_reg_pc + branch_adder_rhs.toUFix;
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@ -18,7 +18,8 @@ class ioALU extends Bundle(){
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class rocketDpathALU extends Component
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{
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override val io = new ioALU();
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val io = new ioALU();
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val out64 =
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MuxCase(Fix(0, 64), Array(
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(io.fn === FN_ADD) -> (io.in1 + io.in2).toFix,
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@ -34,7 +35,7 @@ class rocketDpathALU extends Component
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(io.fn === FN_SRA) -> (io.in1.toFix >>> io.shamt)));
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io.out := MuxLookup(io.dw, Fix(0, 64), Array(
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DW_64 -> out64,
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DW_64 -> out64(63,0),
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DW_32 -> Cat(Fill(32, out64(31)), out64(31,0)).toFix)).toUFix;
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}
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@ -2,11 +2,12 @@ package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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import queues._;
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class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(32, 'output);
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val req_addr = UFix(PADDR_BITS, 'output);
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val req_val = Bool('output);
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val req_rdy = Bool('input);
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val req_tag = Bits(3, 'output);
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@ -83,8 +83,8 @@ class rocketPTW extends Component
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io.itlb.resp_err := (state === s_error);
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io.itlb.resp_perm := r_resp_perm;
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io.itlb.resp_ppn :=
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Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-8, 0)),
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Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-18, 0)),
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Mux(state === s_l1_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-7), r_req_vpn(VPN_BITS-11, 0)),
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Mux(state === s_l2_fake, Cat(r_resp_ppn(PPN_BITS-1, PPN_BITS-17), r_req_vpn(VPN_BITS-21, 0)),
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r_resp_ppn));
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val resp_ptd = (io.dmem.resp_data(1,0) === Bits(1,2));
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