riscv/rocket-chip
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remove host.start signal, use reset instead

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This commit is contained in:
Andrew Waterman 2012-01-11 17:49:32 -08:00
parent 92dda102b6
commit bcb55e581a
3 changed files with 2 additions and 5 deletions
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2
rocket/src/main/scala/cpu.scala
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@ -11,7 +11,6 @@ class ioDebug(view: List[String] = null) extends Bundle(view)
class ioHost(view: List[String] = null) extends Bundle(view)
{
val start = Bool('input);
val from_wen = Bool('input);
val from = Bits(64, 'input);
val to = Bits(64, 'output);
@ -47,7 +46,6 @@ class rocketProc extends Component
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host ^^ io.host;
ctrl.io.host.start := io.host.start;
dpath.io.debug ^^ io.debug;
// FIXME: try to make this more compact

3
rocket/src/main/scala/ctrl.scala
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@ -77,7 +77,6 @@ class ioCtrlAll extends Bundle()
val console = new ioConsole(List("rdy"));
val imem = new ioImem(List("req_val", "req_rdy", "resp_val")).flip();
val dmem = new ioDmem(List("req_val", "req_kill", "req_rdy", "req_cmd", "req_type", "resp_miss", "resp_replay", "resp_nack")).flip();
val host = new ioHost(List("start"));
val dtlb_val = Bool('output);
val dtlb_kill = Bool('output);
val dtlb_rdy = Bool('input);
@ -294,7 +293,7 @@ class rocketCtrl extends Component
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
// FIXME
io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
io.imem.req_val := !io.dpath.xcpt_ma_inst;
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;
val id_mem_val :: id_mem_cmd :: id_mem_type :: id_mul_val :: id_mul_fn :: id_div_val :: id_div_fn :: id_wen :: id_sel_wa :: id_sel_wb :: id_ren_pcr :: id_wen_pcr :: id_irq :: id_sync :: id_eret :: id_syscall :: id_privileged :: Nil = csremainder;

2
rocket/src/main/scala/dpath.scala
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@ -150,7 +150,7 @@ class rocketDpath extends Component
Mux(io.ctrl.sel_pc === PC_MEM, mem_reg_pc,
if_pc_plus4))))))); // PC_4
when (!io.ctrl.stallf && io.host.start) {
when (!io.ctrl.stallf) {
if_reg_pc <== if_next_pc.toUFix;
}