fix WAW hazard handling
This commit is contained in:
Andrew Waterman
parent
eb657dd250
commit
ffe23a1ee8
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@ -103,6 +103,7 @@ class rocketProc extends Component
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ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
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ctrl.io.dmem.resp_nack := arb.io.cpu.resp_nack;
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dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
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dpath.io.dmem.resp_replay := io.dmem.resp_replay;
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dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
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dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
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dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;
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@ -302,10 +302,7 @@ class rocketCtrl extends Component
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val id_raddr2 = io.dpath.inst(21,17);
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val id_raddr1 = io.dpath.inst(26,22);
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val id_waddr = io.dpath.inst(31,27);
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val id_ren2 = id_renx2.toBool;
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val id_ren1 = id_renx1.toBool;
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val id_waddr = Mux(id_sel_wa === WA_RA, RA, io.dpath.inst(31,27));
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val id_console_out_val = id_wen_pcr.toBool && (id_raddr2 === PCR_CONSOLE);
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@ -329,7 +326,6 @@ class rocketCtrl extends Component
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val id_stall_raddr2 = sboard.io.stalla;
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val id_stall_raddr1 = sboard.io.stallb;
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val id_stall_waddr = sboard.io.stallc;
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val id_stall_ra = sboard.io.stallra;
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val id_reg_btb_hit = Reg(resetVal = Bool(false));
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val id_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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@ -581,62 +577,50 @@ class rocketCtrl extends Component
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io.dpath.stalld
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);
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// check for loads and amos in execute and mem stages to detect load/use hazards
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// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
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val ex_mem_cmd_load =
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ex_reg_mem_val && ((ex_reg_mem_cmd === M_XRD) || ex_reg_mem_cmd(3).toBool);
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val lu_stall_ex =
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ex_mem_cmd_load &&
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((id_ren1 && (id_raddr1 === io.dpath.ex_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.ex_waddr)));
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val data_hazard_ex =
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(ex_mem_cmd_load || ex_reg_div_mul_val) &&
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((id_renx1.toBool && (id_raddr1 === io.dpath.ex_waddr)) ||
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(id_renx2.toBool && (id_raddr2 === io.dpath.ex_waddr)) ||
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(id_wen.toBool && (id_waddr === io.dpath.ex_waddr)));
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// stall for RAW/WAW hazards on LB/LH and mul/div in memory stage.
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// stall for WAW-but-not-RAW hazards on LW/LD/AMO.
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val mem_mem_cmd_load =
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mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
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val mem_mem_cmd_load_bh =
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mem_reg_mem_val &&
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(mem_reg_mem_cmd === M_XRD) &&
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mem_mem_cmd_load &&
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((mem_reg_mem_type === MT_B) ||
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(mem_reg_mem_type === MT_BU) ||
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(mem_reg_mem_type === MT_H) ||
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(mem_reg_mem_type === MT_HU));
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val lu_stall_mem =
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mem_mem_cmd_load_bh &&
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((id_ren1 && (id_raddr1 === io.dpath.mem_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.mem_waddr)));
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val raw_hazard_mem =
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(id_renx1.toBool && (id_raddr1 === io.dpath.mem_waddr)) ||
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(id_renx2.toBool && (id_raddr2 === io.dpath.mem_waddr));
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val waw_hazard_mem =
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(id_wen.toBool && (id_waddr === io.dpath.mem_waddr));
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val data_hazard_mem =
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(mem_mem_cmd_load_bh || mem_reg_div_mul_val) && (raw_hazard_mem || waw_hazard_mem) ||
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mem_mem_cmd_load && (!raw_hazard_mem && waw_hazard_mem)
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val lu_stall_wb =
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dcache_miss &&
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((id_ren1 && (id_raddr1 === io.dpath.wb_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.wb_waddr)));
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// stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback.
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val data_hazard_wb =
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(dcache_miss || wb_reg_div_mul_val) &&
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((id_renx1.toBool && (id_raddr1 === io.dpath.wb_waddr)) ||
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(id_renx2.toBool && (id_raddr2 === io.dpath.wb_waddr)) ||
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(id_wen.toBool && (id_waddr === io.dpath.wb_waddr)));
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val lu_stall = lu_stall_ex || lu_stall_mem || lu_stall_wb;
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// check for divide and multiply instructions in ex,mem,wb stages
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val dm_stall_ex =
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ex_reg_div_mul_val &&
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((id_ren1 && (id_raddr1 === io.dpath.ex_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.ex_waddr)));
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val dm_stall_mem =
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mem_reg_div_mul_val &&
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((id_ren1 && (id_raddr1 === io.dpath.mem_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.mem_waddr)));
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val dm_stall_wb =
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wb_reg_div_mul_val &&
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((id_ren1 && (id_raddr1 === io.dpath.wb_waddr)) ||
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(id_ren2 && (id_raddr2 === io.dpath.wb_waddr)));
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val dm_stall = dm_stall_ex || dm_stall_mem || dm_stall_wb;
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val data_hazard = data_hazard_ex || data_hazard_mem || data_hazard_wb;
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val ctrl_stalld =
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!take_pc &&
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(
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dm_stall ||
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lu_stall ||
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id_ren2 && id_stall_raddr2 ||
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id_ren1 && id_stall_raddr1 ||
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(id_sel_wa === WA_RD) && id_stall_waddr ||
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(id_sel_wa === WA_RA) && id_stall_ra ||
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data_hazard ||
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id_renx2.toBool && id_stall_raddr2 ||
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id_renx1.toBool && id_stall_raddr1 ||
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id_wen.toBool && id_stall_waddr ||
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id_mem_val.toBool && !(io.dmem.req_rdy && io.dtlb_rdy) ||
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((id_sync === SYNC_D) || (id_sync === SYNC_I)) && !io.dmem.req_rdy ||
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id_console_out_val && !io.console.rdy ||
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@ -662,8 +646,8 @@ class rocketCtrl extends Component
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io.dpath.killm := kill_mem;
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io.dpath.mem_load := mem_reg_mem_val && ((mem_reg_mem_cmd === M_XRD) || mem_reg_mem_cmd(3).toBool);
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io.dpath.ren2 := id_ren2;
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io.dpath.ren1 := id_ren1;
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io.dpath.ren2 := id_renx2.toBool;
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io.dpath.ren1 := id_renx1.toBool;
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io.dpath.sel_alu2 := id_sel_alu2;
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io.dpath.sel_alu1 := id_sel_alu1.toBool;
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io.dpath.fn_dw := id_fn_dw.toBool;
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@ -18,7 +18,6 @@ class ioCtrlSboard extends Bundle()
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val stalla = Bool('output);
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val stallb = Bool('output);
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val stallc = Bool('output);
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val stallra = Bool('output);
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}
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class rocketCtrlSboard extends Component
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@ -34,7 +33,6 @@ class rocketCtrlSboard extends Component
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io.stalla := reg_busy(io.raddra).toBool;
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io.stallb := reg_busy(io.raddrb).toBool;
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io.stallc := reg_busy(io.raddrc).toBool;
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io.stallra := reg_busy(RA).toBool;
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}
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class ioCtrlCnt extends Bundle()
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@ -21,6 +21,7 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
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val resp_miss = Bool('output);
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val resp_nack = Bool('output);
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val resp_val = Bool('output);
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val resp_replay = Bool('output);
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val resp_data = Bits(64, 'output);
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val resp_data_subword = Bits(64, 'output);
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val resp_tag = Bits(DCACHE_TAG_BITS, 'output);
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@ -11,6 +11,7 @@ class ioDpathDmem extends Bundle()
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val req_tag = UFix(CPU_TAG_BITS, 'output);
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val req_data = Bits(64, 'output);
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val resp_val = Bool('input);
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val resp_replay = Bool('input);
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val resp_tag = Bits(CPU_TAG_BITS, 'input);
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val resp_data = Bits(64, 'input);
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val resp_data_subword = Bits(64, 'input);
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@ -770,6 +770,7 @@ class HellaCache(lines: Int) extends Component {
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io.cpu.req_rdy := flusher.io.req.ready && !(r_cpu_req_val_ && r_req_flush) && !pending_fence
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io.cpu.resp_nack := r_cpu_req_val_ && !io.cpu.req_kill && nack
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io.cpu.resp_val := (tag_hit && !nack_hit && r_req_read) || replayer.io.cpu_resp_val
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io.cpu.resp_replay := replayer.io.cpu_resp_val
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io.cpu.resp_miss := tag_miss && !nack_miss && r_req_read
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io.cpu.resp_tag := Mux(replayer.io.cpu_resp_val, replayer.io.cpu_resp_tag, r_cpu_req_tag)
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io.cpu.resp_data := loadgen.io.dout
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