96fa1eb6ad
Add UInt->BitPat implicit conversion
...
This will be removed from Chisel3, so we're putting it here to maintain
compatibility.
2016-05-26 18:52:53 -07:00
0c50bfcfb3
Work around more zero-width wire cases
2016-05-25 21:47:48 -07:00
40f38dde63
Work around lack of zero-width wires in D$
2016-05-25 19:44:31 -07:00
00ea9a7d82
Remove most of mstatus when user mode isn't supported
2016-05-25 15:37:32 -07:00
5442b89664
Remove unnecessary muxes in RV32 MulDiv
2016-05-25 14:27:02 -07:00
9aa724706e
Don't include RV64 instructions in RV32 decode table
2016-05-25 14:26:45 -07:00
4605b616c1
Fix bug in D$ AMO/storegen logic
2016-05-24 16:26:07 -07:00
5dac7b818d
Support set associativity in blocking D$
2016-05-24 15:45:52 -07:00
e0addb5723
Support uncached AMOs in blocking D$
2016-05-24 15:45:35 -07:00
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
3b35c7470e
Add uncached support to blocking D$
2016-05-24 15:05:41 -07:00
42f079ce57
JAL requires DW_XPR
...
This has been benign so far because of how the logic minimization worked.
2016-05-24 15:05:41 -07:00
b92c73e361
Add LR/SC to blocking D$
2016-05-24 15:05:41 -07:00
0d93d1a1a0
Clean up pending store logic a bit
2016-05-24 15:05:41 -07:00
0b8de578d4
Add additional D$ store buffering to prevent structural hazards
2016-05-24 15:05:41 -07:00
354cb2d5ec
Don't stall I$ response when resolving a branch misprediction
...
This avoids a fetch bubble.
Not clear if this is the best way to do it. Perhaps this change should
instead be made to Frontend (i.e., ignore resp.ready when req.valid is
high), but that might exacerbate a critical path.
2016-05-24 15:05:41 -07:00
d7790ac6a4
WIP on blocking D$
2016-05-24 15:05:41 -07:00
335e2c8a1e
Support disabling atomics extension
2016-05-24 15:05:41 -07:00
765b90f6a4
Stall on D$ lockups less conservatively
2016-05-24 15:05:41 -07:00
a3061047e3
Instantiate blocking D$ when NMSHRS=0
2016-05-24 15:05:41 -07:00
80482890fd
Don't rely on tag value for nacks
2016-05-24 15:05:41 -07:00
e19c5e5d2c
IOMSHR: support atomic operations
2016-05-24 15:00:50 -07:00
7bc38383de
add (non-working) blocking data cache
2016-05-20 18:59:05 -07:00
f228309bd1
add assertion to make sure SimpleHellaCacheIF doesn't get exception
2016-05-20 16:30:27 -07:00
4aef567a80
Fix MMIO bug: replay_next wasn't set
2016-05-13 17:59:53 -07:00
742c05d6a7
Pipeline D$->I$ control paths
...
These stretch the miss latency by a cycle in exchange for slack.
The current implementation also adds a cycle to mul/div latency,
which can be worked around for more hardware (possibly gated by
the FastMulDiv option).
2016-05-13 17:07:28 -07:00
8fa2de0816
chisel3 fix to RoCC connections honor last connect
2016-05-05 18:09:48 -07:00
9dd23a603a
Remove HTIF port
2016-05-03 13:41:58 -07:00
5352497edb
MPRV takes effect regardless of privilege mode
2016-05-02 19:53:25 -07:00
5cbcc41515
get rid of unused imports
2016-05-02 18:23:46 -07:00
f784f4da93
Rename PRCICoreIO to PRCITileIO
2016-05-02 18:08:01 -07:00
000e20f937
Remove MIPI; make mip.MSIP read-only
...
The PRCI block outside the core will provide IPIs eventually
2016-05-02 15:18:41 -07:00
83fa489cef
Stop using HTIF CSR port
...
The port itself is still present to keep other stuff compiling.
2016-05-02 14:40:52 -07:00
0ff4fd0ccd
Fix IOMSHR to send finishes for stores
2016-04-30 22:20:29 -07:00
491184a8f8
ERET -> xRET; remove mcfgaddr
2016-04-30 17:32:51 -07:00
5af98145b9
don't signal bad physical address on TLB miss
2016-04-30 17:31:46 -07:00
cae4265f3b
Change mcfgaddr pointer
2016-04-28 16:14:05 -07:00
739cf07637
Remove mtime/mtimecmp
...
The RTC is now a device that lives on the MMIO bus.
2016-04-27 14:54:51 -07:00
fb5c38c186
Handle invalidate_lr in cache arbiter, not tile
2016-04-27 11:22:04 -07:00
b99db83e67
Avoid needless Vec generation
2016-04-27 00:28:39 -07:00
8acec8eb36
Remove dead code from BTB
2016-04-27 00:28:12 -07:00
fe8c91f620
Fix IOMSHR state machine bug
...
Sending the finish too early causes the CPU response to get dropped.
attn @zhemao
2016-04-26 15:32:25 -07:00
5fd5b58743
Remove stats CSR
2016-04-26 15:31:32 -07:00
d93677a343
Support larger cache sets when not using VM
2016-04-26 15:31:32 -07:00
5dbf9640e2
Use TLB flush signal to I$ explicitly
2016-04-22 15:41:31 -07:00
84fd45fd77
Pass TLB flush signal to I$ explicitly
2016-04-22 15:20:17 -07:00
b7527268bb
use address map instead of MMIOBase to find size of memory
2016-04-21 18:44:39 -07:00
2d6f35525e
Added Field[Int] to SFMALatency/DFMALatency params
2016-04-06 14:50:57 -07:00
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
dc662f28a0
Specify width on s1_pc to avoid width inference problem
2016-04-01 17:28:42 -07:00
