riscv/rocket-chip
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170 Commits

Author SHA1 Message Date
Rimas Avizienis
63060bc0a8 minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc) 2013-01-23 19:27:53 -08:00
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Andrew Waterman
de2f28193a get rid of more global constants 2012-11-25 04:24:25 -08:00
Andrew Waterman
b514c7b725 clean up I$ parity code 2012-11-24 22:00:43 -08:00
Andrew Waterman
ff8c736d94 move icache invalidate out of request bundle 2012-11-16 01:55:45 -08:00
Andrew Waterman
4d1ca8ba3a remove more global consts; refactor DTLBs 
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
 2012-11-06 08:13:44 -08:00
Andrew Waterman
c5b93798fb factor out more global constants 2012-11-05 23:52:32 -08:00
Andrew Waterman
e9eca6a95d refactor I$ config; remove Top class 2012-11-04 16:59:36 -08:00
Andrew Waterman
bd2d61de03 use 8T SRAM for I$; gate clock more aggressively 2012-11-04 16:39:25 -08:00
Henry Cook
88ac5af181 Merged consts-as-traits 2012-10-16 16:32:35 -07:00
Andrew Waterman
5821900329 don't refetch from I$ if on same 16B block 2012-10-16 02:24:38 -07:00
Andrew Waterman
661f8e635b merge I$, ITLB, BTB into Frontend 2012-10-16 02:24:37 -07:00
Henry Cook
8970b635b2 improvements to implicit RocketConfiguration parameter 2012-10-15 16:29:49 -07:00
Henry Cook
9025d0610c first pass at configuration object passed as implicit parameter 2012-10-07 22:37:29 -07:00
Henry Cook
dfdfddebe8 constants as traits 2012-10-07 22:20:03 -07:00
Huy Vo
e909093f37 factoring out uncore into separate uncore repo 2012-10-01 16:08:41 -07:00
Henry Cook
b9a9664de5 uncore and rocket changes for new xact types 2012-10-01 10:47:36 -07:00
Andrew Waterman
0f20771664 rename queue to Queue 
fixes build with case-insensitive file system
 2012-08-08 22:11:59 -07:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3 use only one (wide) tag ram for set assoc. caches 2012-07-12 14:50:12 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44 views removed 2012-06-06 12:51:26 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
7408c9ab69 removing wires 2012-05-24 10:42:39 -07:00
Andrew Waterman
eafdffe125 simplify page table walker; speed up emulator 2012-05-01 01:24:36 -07:00
Henry Cook
3cdd166153 Refactored coherence as member rather than trait. MI and MEI protocols. 2012-04-10 00:09:58 -07:00
Henry Cook
0b4937f70f changed coherence message type names 2012-04-09 23:29:31 -07:00
Yunsup Lee
32d95e9594 fix -1:0 index problem for direct map case 2012-03-26 17:00:01 -07:00
Henry Cook
22726ae646 icache and htif now obey require_ack field of TransactionReply. Avoids extraneous TransactionFinish on prefetcher-supplied icache data 2012-03-08 18:47:32 -08:00
Andrew Waterman
6e16b04ada implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman
5f12990dfb support memory transaction aborts 2012-03-06 00:35:02 -08:00
Henry Cook
1b3307df32 Removed has_data fields from all coherence messages, increased message type names to compensate 2012-03-02 23:51:53 -08:00
Andrew Waterman
012da6002e replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman
c99f6bbeb7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman
2b1c07c723 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman
ad713a5d83 fix icache ram depth; new chisel 2012-02-26 17:51:46 -08:00
Huy Vo
5b0f7ccf68 updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit 2012-02-26 17:24:08 -08:00
Yunsup Lee
94ba32bbd3 change package name and sbt project name to rocket 2012-02-25 17:09:26 -08:00
Andrew Waterman
6135615104 unify cache backend interfaces; generify arbiter 2012-02-20 00:51:48 -08:00
Andrew Waterman
725190d0ee update to new chisel 2012-02-11 17:20:33 -08:00
Christopher Celio
1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache 2012-02-07 14:07:42 -08:00
Henry Cook
c5a4eaa0a1 Associative cache, boots kernel 2012-02-01 13:26:04 -08:00
Andrew Waterman
97c379f1d7 made I$ associative 2012-01-24 16:51:30 -08:00
Andrew Waterman
7f26fe2c44 make icache size parameterizable 2012-01-24 15:13:49 -08:00
Andrew Waterman
a5a020f97b update chisel and remove SRAM_READ_LATENCY 2012-01-23 20:59:38 -08:00
Henry Cook
1d76255dc1 new chisel version jar and find and replace INPUT and OUTPUT 2012-01-18 14:39:57 -08:00
Andrew Waterman
addfe55735 add FPGA memory generator script 2012-01-13 18:19:08 -08:00
Andrew Waterman
4807d7222b use replay to handle I$ misses 
this eliminates a long path in the fetch stage
 2012-01-11 19:20:20 -08:00
Andrew Waterman
1a7bfd4350 remove icache req_rdy signal 2012-01-11 18:27:11 -08:00
Andrew Waterman
a8d0cd95e6 hellacache now works 2011-12-17 03:26:11 -08:00
Andrew Waterman
56c4f44c2a hellacache returns! 
but AMOs are unimplemented.
 2011-12-12 06:49:39 -08:00
Andrew Waterman
218f63e66e code cleanup/parameterization 2011-12-09 00:42:43 -08:00
Rimas Avizienis
fa784d1d7d made setReadLatency argument a parameter defined in consts.scala 2011-12-05 00:33:17 -08:00
Rimas Avizienis
ff95cacb55 icache/dcache tag+data arrays now implemented using Mem4() 
however there seems to be a bug - readLatency needs to be set to 0
for C model to work, and 1 for Verilog model.
 2011-12-04 01:18:38 -08:00
Rimas Avizienis
e894b79870 caches now use Mem4() memories for tag+data arrays 2011-12-03 19:41:15 -08:00
Rimas Avizienis
c580180b66 tweaks to cache/SRAM interface for TSMC65 SRAMs 2011-12-02 02:01:08 -08:00
Rimas Avizienis
cf1965493b renamed SRAM modules to match TSMC65 MC generated SRAMs 2011-12-01 13:14:33 -08:00
Rimas Avizienis
b791010bb1 flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs 2011-11-14 04:13:13 -08:00
Rimas Avizienis
35af912bd2 cache optimizations, cleanup, and testharness improvement 2011-11-12 22:13:29 -08:00
Rimas Avizienis
83d90c4dab more itlb/dtlb/ptw fixes 2011-11-12 15:00:45 -08:00
Rimas Avizienis
73416f224b more tlb/ptw debugging 2011-11-12 00:25:06 -08:00
Rimas Avizienis
36aa4bcc9d moved exception handling from ex stage in dpath to mem stage in ctrl 2011-11-10 02:26:26 -08:00
Rimas Avizienis
c29d2821b4 cleanup, fixes, initial commit for dtlb.scala 2011-11-09 21:54:11 -08:00
Rimas Avizienis
e96430d862 integrating ITLB & PTW 2011-11-09 14:52:17 -08:00
Rimas Avizienis
9d63087eb2 changed caches to use separate sram modules for tag and data arrays 2011-11-07 00:58:25 -08:00
Rimas Avizienis
4d64099103 cleanup 2011-11-04 20:52:21 -07:00
Rimas Avizienis
c06e2d16e4 initial commit of rocket chisel project, riscv assembly tests and benchmarks 2011-10-25 23:02:47 -07:00