icache/dcache tag+data arrays now implemented using Mem4()
however there seems to be a bug - readLatency needs to be set to 0 for C model to work, and 1 for Verilog model.
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@ -252,8 +252,6 @@ class rocketDCacheDM(lines: Int) extends Component {
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val tag_array = Mem4(lines, r_cpu_req_ppn);
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tag_array.setReadLatency(0);
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
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// tag_array.write(tag_addr, r_cpu_req_ppn, tag_we);
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// val tag_rdata = tag_array(tag_addr);
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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@ -370,8 +368,6 @@ class rocketDCacheDM(lines: Int) extends Component {
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val data_array = Mem4(lines*4, data_wdata);
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data_array.setReadLatency(0);
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val data_array_rdata = data_array.rw(data_addr, data_wdata, data_we, data_wmask);
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// data_array.write(data_addr, data_wdata, data_we, data_wmask);
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// val data_array_rdata = data_array(data_addr);
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val resp_data = Mux(r_cpu_req_idx(offsetlsb).toBool, data_array_rdata(127, 64), data_array_rdata(63,0));
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val r_resp_data = Reg(resp_data);
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@ -86,10 +86,7 @@ class rocketICacheDM(lines: Int) extends Component {
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val tag_array = Mem4(lines, r_cpu_req_ppn);
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tag_array.setReadLatency(0);
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val tag_rdata = tag_array.rw(tag_addr, r_cpu_req_ppn, tag_we);
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// tag_array.write(tag_addr, r_cpu_req_ppn, tag_we);
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// val tag_rdata = tag_array.read(tag_addr);
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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when (io.cpu.invalidate) {
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@ -109,8 +106,6 @@ class rocketICacheDM(lines: Int) extends Component {
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val data_array = Mem4(lines*4, io.mem.resp_data);
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data_array.setReadLatency(0);
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val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
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// data_array.write(data_addr, io.mem.resp_data, io.mem.resp_val);
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// val data_array_rdata = data_array.read(data_addr);
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// output signals
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match;
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