832e56d3c7
Fix toBits/toUInt/toSInt deprecation warnings
2016-07-31 17:13:52 -07:00
d78f1aacd0
Clean up some zero-width wire cases using UInt.extract
2016-07-14 22:08:01 -07:00
e6aab368a4
Replace ICacheBufferWays parameter with I$ constructor argument
2016-07-14 12:38:54 -07:00
1699622730
Don't speculatively refill I$ in uncacheable regions
2016-07-09 01:10:58 -07:00
a9e0a5e2df
changes to imports after uncore refactor
2016-06-28 14:09:31 -07:00
f14d87e327
Support larger I$ sets when VM is disabled
2016-05-24 15:44:59 -07:00
51e0870e23
Separate I$ and D$ interface signals that span clock cycles
...
For example, Decopuled[HellaCacheReq].bits.kill doesn't make sense,
since it doesn't come the same cycle as ready/valid.
2016-04-01 19:30:39 -07:00
ed280fb3de
Remove empty when statement (???)
2016-03-25 15:52:18 -07:00
58fcc6b7c6
Get rid of useless mux
2016-01-28 11:44:59 -08:00
13ce91e453
fix Chisel3 compat warnings in ICache and FPU
2016-01-12 12:43:48 -08:00
7690de07e1
allow icache to configure which side of the way mux gets buffered
2015-12-02 17:17:49 -08:00
652fb393a3
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-22 16:38:28 -07:00
4f8468b60f
depend on external cde library
2015-10-21 18:19:23 -07:00
97f29b1618
Merge remote-tracking branch 'origin/master' into rocc-fpu-port
2015-10-21 11:33:42 -07:00
1a1185be3f
Vectorize ROCC and Tile memory interfaces
2015-10-20 15:02:24 -07:00
2cee8c8bec
Merge commit '3c3e35a56e954b35e6ceb17179ebadc52e8d9b3f' into rocc-fpu-port
2015-10-18 13:09:17 -07:00
68cb54bc68
refactor tilelink params
2015-10-14 12:14:36 -07:00
84576650b5
Removed all traces of params
2015-10-05 21:48:05 -07:00
c3fff12ff0
Revert "replace remaining uses of Vec.fill"
...
This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
2015-09-25 17:09:06 -07:00
a66bdb1956
replace remaining uses of Vec.fill
2015-09-24 17:53:26 -07:00
9eb988a4c6
make sure access to invalid physical address treated as exception
2015-09-22 10:11:43 -07:00
78b2e947de
Chisel3 compatibility fixes
2015-09-11 15:43:07 -07:00
cab12635f8
Merge master into rocc-fpu-port
...
ebb33f2f4b658211960a4c6c023c139420c67212
2015-08-06 08:03:10 -07:00
546205b174
Chisel3 compatibility: use >>Int instead of >>UInt
2015-08-05 15:29:03 -07:00
52fc34a138
Chisel3: bulk connect is not commutative
...
We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:11:25 -07:00
6d7cc37e87
Specify some uninferrable widths
...
It's really scary that Chisel2 passed this stuff.
2015-07-31 14:23:52 -07:00
57930e8a26
Chisel3 compatibility potpourri
2015-07-30 23:53:02 -07:00
ac6e73e317
Add Wire() wrap
2015-07-15 20:24:18 -07:00
5b7f3c3006
Don't use clone
2015-07-15 17:30:50 -07:00
be2ff6dec7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:33:46 -07:00
3233867390
Use Chisel3 SeqMem construct
2015-07-11 13:34:57 -07:00
4b6cd7f3eb
Merge branch 'master' of ucb-bar/rocket into rocc-fpu-port for priv1.7
2015-06-03 15:51:53 -07:00
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
b09832f1b5
ICache now returns the "next PC" signal.
...
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
a37fad2e9b
Merge branch 'retimeable-frontend' into rocc-fpu-port
2015-04-22 14:23:52 -07:00
1f410ac42c
move fetch buffer into frontend to allow retiming
2015-04-22 11:26:03 -07:00
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
543ac91cf2
Misaligned fetches can't happen at the I$ anymore
...
They are caught before the I$ ever sees them, so leverage that fact.
2015-03-24 23:55:43 -07:00
e85c54cc4b
New privileged ISA implementation
2015-03-14 02:49:07 -07:00
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
b70f7683d3
Merge branch 'master' into ss-frontend
...
Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
2aee85cb11
Flush pipeline from MEM stage
...
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
1cb65d5ec1
%s/master/manager/g
2014-12-29 22:56:18 -08:00
