132 lines
4.3 KiB
Scala
132 lines
4.3 KiB
Scala
package Top {
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import Chisel._
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import Node._;
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import scala.math._;
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// interface between I$ and processor (32 bits wide)
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class ioImem(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(32, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val resp_data = Bits(32, 'output);
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val resp_val = Bool('output);
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}
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// interface between I$ and memory (128 bits wide)
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class ioIcache(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(32, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val resp_data = Bits(128, 'output);
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val resp_val = Bool('output);
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}
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class ioICacheDM extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioIcache().flip();
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}
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// basic direct mapped instruction cache
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// parameters :
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// lines = # cache lines
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// addr_bits = address width (word addressable) bits
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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class rocketICacheDM(lines: Int, addrbits : Int) extends Component {
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val io = new ioICacheDM();
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 2;
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_reset);
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val r_cpu_req_addr = Reg(Bits(0, addrbits));
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when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
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r_cpu_req_addr <== io.cpu.req_addr;
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}
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val r_cpu_req_val = Reg(Bool(false));
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when ((state === s_ready) || (state === s_resolve_miss)) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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val refill_count = Reg(resetVal = UFix(0,2));
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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}
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// tag array
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val tag_wdata = r_cpu_req_addr(tagmsb, taglsb);
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val tag_waddr = r_cpu_req_addr(indexmsb, indexlsb).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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val tag_array = Mem(lines, tag_we, tag_waddr, tag_wdata);
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val tag_raddr = io.cpu.req_addr(indexmsb, indexlsb);;
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val tag_lookup = Reg(tag_array.read(tag_raddr));
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
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when ((state === s_refill_wait) && io.mem.resp_val) {
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vb_array <== vb_array.bitSet(r_cpu_req_addr(indexmsb, indexlsb).toUFix, UFix(1,1));
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}
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val tag_match = vb_rdata.toBool && (tag_lookup === r_cpu_req_addr(tagmsb, taglsb));
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// data array
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val data_array_waddr = Cat(r_cpu_req_addr(indexmsb, indexlsb), refill_count).toUFix;
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val data_array = Mem(lines*4, io.mem.resp_val, data_array_waddr, io.mem.resp_data);
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val data_array_raddr = Cat(io.cpu.req_addr(indexmsb, indexlsb), io.cpu.req_addr(offsetmsb, offsetmsb-1));
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val data_array_read = data_array(data_array_raddr);
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val data_array_rdata = Reg(data_array_read);
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io.cpu.resp_val := (r_cpu_req_val && tag_match && (state === s_ready)); // || (state === s_resolve_miss);
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io.cpu.req_rdy := ((state === s_ready) && (!r_cpu_req_val || (r_cpu_req_val && tag_match))); // || (state === s_resolve_miss);
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io.cpu.resp_data := MuxLookup(r_cpu_req_addr(offsetmsb-2, offsetlsb).toUFix, data_array_rdata(127, 96),
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Array(UFix(2) -> data_array_rdata(95,64),
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UFix(1) -> data_array_rdata(63,32),
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UFix(0) -> data_array_rdata(31,0)));
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io.mem.req_val := (state === s_request);
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io.mem.req_addr := Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix;
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// control state machine
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switch (state) {
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is (s_reset) {
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state <== s_ready;
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}
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is (s_ready) {
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when (r_cpu_req_val && !tag_match) { state <== s_request; }
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}
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is (s_request)
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{
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when (io.mem.req_rdy) { state <== s_refill_wait; }
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}
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is (s_refill_wait) {
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when (io.mem.resp_val) { state <== s_refill; }
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}
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is (s_refill) {
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when (io.mem.resp_val && (refill_count === UFix(3,2))) { state <== s_resolve_miss; }
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}
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is (s_resolve_miss) {
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state <== s_ready;
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}
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}
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}
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}
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