212 lines
6.4 KiB
Scala
212 lines
6.4 KiB
Scala
package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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// interface between I$ and pipeline/ITLB (32 bits wide)
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class ioImem(view: List[String] = null) extends Bundle (view)
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{
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val invalidate = Bool('input);
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val itlb_miss = Bool('input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_idx = Bits(PGIDX_BITS, 'input);
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val req_ppn = Bits(PPN_BITS, 'input);
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val resp_data = Bits(32, 'output);
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val resp_val = Bool('output);
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}
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// interface between I$ and memory (128 bits wide)
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class ioIcache(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(PADDR_BITS, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val resp_data = Bits(128, 'output);
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val resp_val = Bool('output);
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}
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class ioICacheDM extends Bundle()
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{
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val cpu = new ioImem();
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val mem = new ioIcache().flip();
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}
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// single port SRAM i/o
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class ioSRAMsp (width: Int, addrbits: Int) extends Bundle {
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val a = UFix(addrbits, 'input); // address
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val d = Bits(width, 'input); // data input
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val bweb = Bits(width, 'input); // bit write enable mask
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val ceb = Bool('input); // chip enable
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val web = Bool('input); // write enable
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val q = Bits(width, 'output); // data out
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val tsel = Bits(2, 'input);
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}
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// single ported SRAM
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class TS1N65LPA128X27M4 extends Component {
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val addrbits = 7;
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val width = 27;
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val entries = 128;
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val io = new ioSRAMsp(width, addrbits);
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val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
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val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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}
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class TS1N65LPA512X128M4 extends Component {
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val addrbits = 9;
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val width = 128;
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val entries = 512;
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val io = new ioSRAMsp(width, addrbits);
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val sram = Mem(entries, ~io.web, io.a, io.d, wrMask = ~io.bweb, resetVal = null);
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val rdata = Reg(Mux(~io.ceb, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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}
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/*
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class rocketSRAMsp(entries: Int, width: Int) extends Component {
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val addrbits = ceil(log10(entries)/log10(2)).toInt;
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val io = new ioSRAMsp(width, addrbits);
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val sram = Mem(entries, io.we, io.a, io.d, wrMask = io.bweb, resetVal = null);
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val rdata = Reg(Mux(io.ce, sram.read(io.a), Bits(0,width)));
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io.q := rdata;
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}
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*/
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// basic direct mapped instruction cache
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// 32 bit wide cpu port, 128 bit wide memory port, 64 byte cachelines
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// parameters :
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// lines = # cache lines
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class rocketICacheDM(lines: Int) extends Component {
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val io = new ioICacheDM();
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val addrbits = PADDR_BITS;
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val indexbits = ceil(log10(lines)/log10(2)).toInt;
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val offsetbits = 6;
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val tagmsb = addrbits - 1;
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val taglsb = indexbits+offsetbits;
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val tagbits = addrbits-taglsb;
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 2;
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val databits = 32;
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_reset);
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val r_cpu_req_idx = Reg(resetVal = Bits(0, PGIDX_BITS));
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val r_cpu_req_ppn = Reg(resetVal = Bits(0, PPN_BITS));
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val r_cpu_req_val = Reg(resetVal = Bool(false));
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when (io.cpu.req_val && io.cpu.req_rdy) {
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r_cpu_req_idx <== io.cpu.req_idx;
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}
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when (state === s_ready && r_cpu_req_val && !io.cpu.itlb_miss) {
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r_cpu_req_ppn <== io.cpu.req_ppn;
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}
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when (io.cpu.req_rdy) {
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r_cpu_req_val <== io.cpu.req_val;
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}
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otherwise {
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r_cpu_req_val <== Bool(false);
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}
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// refill counter
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val refill_count = Reg(resetVal = UFix(0,2));
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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}
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// tag array
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// val tag_array = new rocketSRAMsp(lines, tagbits);
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val tag_array = new TS1N65LPA128X27M4;
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val tag_addr =
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Mux((state === s_refill_wait), r_cpu_req_idx(PGIDX_BITS-1,offsetbits),
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io.cpu.req_idx(PGIDX_BITS-1,offsetbits)).toUFix;
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val tag_we = (state === s_refill_wait) && io.mem.resp_val;
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tag_array.io.a := tag_addr;
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tag_array.io.d := r_cpu_req_ppn;
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tag_array.io.web := ~tag_we;
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tag_array.io.tsel := Bits(1,2);
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tag_array.io.bweb := Bits(0,tagbits);
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tag_array.io.ceb := !(io.cpu.req_val && io.cpu.req_rdy);
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val tag_rdata = tag_array.io.q;
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// valid bit array
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val vb_array = Reg(resetVal = Bits(0, lines));
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when (io.cpu.invalidate) {
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vb_array <== Bits(0,lines);
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}
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when (tag_we) {
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vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
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}
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val tag_valid = Reg(vb_array(tag_addr)).toBool;
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val tag_match = (tag_rdata === io.cpu.req_ppn);
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// data array
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// val data_array = new rocketSRAMsp(lines*4, 128);
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val data_array = new TS1N65LPA512X128M4;
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data_array.io.a :=
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
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data_array.io.d := io.mem.resp_data;
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data_array.io.web := ~io.mem.resp_val;
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data_array.io.bweb := Bits(0,128);
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data_array.io.tsel := Bits(1,2);
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data_array.io.ceb := !((io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss));
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val data_array_rdata = data_array.io.q;
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// output signals
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match;
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io.cpu.req_rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
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io.cpu.resp_data :=
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MuxLookup(r_cpu_req_idx(offsetmsb-2, offsetlsb).toUFix, data_array_rdata(127, 96),
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Array(UFix(2) -> data_array_rdata(95,64),
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UFix(1) -> data_array_rdata(63,32),
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UFix(0) -> data_array_rdata(31,0)));
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io.mem.req_val := (state === s_request);
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
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// control state machine
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switch (state) {
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is (s_reset) {
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state <== s_ready;
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}
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is (s_ready) {
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when (io.cpu.itlb_miss) {
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state <== s_ready;
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}
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when (r_cpu_req_val && !(tag_valid && tag_match)) {
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state <== s_request;
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}
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}
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is (s_request)
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{
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when (io.mem.req_rdy) {
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state <== s_refill_wait;
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}
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}
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is (s_refill_wait) {
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when (io.mem.resp_val) {
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state <== s_refill;
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}
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}
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is (s_refill) {
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when (io.mem.resp_val && (refill_count === UFix(3,2))) {
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state <== s_resolve_miss;
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}
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}
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is (s_resolve_miss) {
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state <== s_ready;
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}
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}
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}
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}
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