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cache optimizations, cleanup, and testharness improvement

This commit is contained in:
Rimas Avizienis 2011-11-12 22:13:29 -08:00
parent 91c252ad08
commit 35af912bd2
3 changed files with 10 additions and 23 deletions
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1
rocket/src/main/scala/ctrl.scala
View File

@ -196,6 +196,7 @@ class rocketCtrl extends Component
val if_reg_xcpt_ma_inst = Reg(io.dpath.xcpt_ma_inst);
// FIXME
// io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
io.imem.req_val := io.host.start && !io.dpath.xcpt_ma_inst;
val id_int_val :: id_br_type :: id_renx2 :: id_renx1 :: id_sel_alu2 :: id_sel_alu1 :: id_fn_dw :: id_fn_alu :: csremainder = cs;

13
rocket/src/main/scala/dcache.scala
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@ -251,12 +251,14 @@ class rocketDCacheDM(lines: Int) extends Component {
tag_array.io.d := r_cpu_req_ppn;
tag_array.io.we := tag_we;
tag_array.io.bweb := ~Bits(0,tagbits);
tag_array.io.ce := (state === s_ready) || (state === s_start_writeback) || (state === s_writeback);
tag_array.io.ce :=
(io.cpu.req_val && io.cpu.req_rdy) ||
(state === s_start_writeback) ||
(state === s_writeback);
val tag_rdata = tag_array.io.q;
// valid bit array
val vb_array = Reg(resetVal = Bits(0, lines));
// val vb_rdata = Reg(vb_array(tag_raddr));
when (tag_we && !r_req_flush) {
vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
}
@ -265,9 +267,10 @@ class rocketDCacheDM(lines: Int) extends Component {
}
val vb_rdata = Reg(vb_array(tag_addr).toBool);
val tag_valid = r_cpu_req_val && vb_rdata;
// val tag_valid = Reg(vb_array(tag_addr)).toBool;
val tag_match = (tag_rdata === io.cpu.req_ppn);
val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetbits) === p_store_idx(PGIDX_BITS-1,offsetbits));
// load/store addresses conflict if they are to any part of the same 64 bit word
val addr_match = (r_cpu_req_idx(PGIDX_BITS-1,offsetlsb) === p_store_idx(PGIDX_BITS-1,offsetlsb));
val ldst_conflict = r_cpu_req_val && r_req_load && p_store_valid && addr_match;
// write the pending store data when the cache is idle, when the next command isn't a load
@ -281,7 +284,6 @@ class rocketDCacheDM(lines: Int) extends Component {
// dirty bit array
val db_array = Reg(resetVal = Bits(0, lines));
// val db_rdata = Reg(db_array(tag_raddr));
val tag_dirty = Reg(db_array(tag_addr)).toBool;
when (io.cpu.req_val && io.cpu.req_rdy && req_store) {
@ -328,7 +330,6 @@ class rocketDCacheDM(lines: Int) extends Component {
data_array.io.d := Mux((state === s_refill), io.mem.resp_data, store_data);
data_array.io.we := ((state === s_refill) && io.mem.resp_val) || drain_store || resolve_store;
data_array.io.bweb := Mux((state === s_refill), ~Bits(0,128), store_wmask);
// data_array.io.ce := Bool(true); // FIXME
data_array.io.ce :=
(io.cpu.req_val && io.cpu.req_rdy && req_load) ||
(state === s_start_writeback) ||

19
rocket/src/main/scala/icache.scala
View File

@ -90,20 +90,8 @@ class rocketICacheDM(lines: Int) extends Component {
otherwise {
r_cpu_req_val <== Bool(false);
}
// val r_cpu_req_addr = Reg(Bits(0, addrbits));
// when (io.cpu.req_val && ((state === s_ready) || (state === s_resolve_miss))) {
// r_cpu_req_addr <== io.cpu.req_addr;
// }
// val r_cpu_req_val = Reg(Bool(false));
// when ((state === s_ready) || (state === s_resolve_miss)) {
// r_cpu_req_val <== io.cpu.req_val;
// }
// otherwise {
// r_cpu_req_val <== Bool(false);
// }
// refill counter
val refill_count = Reg(resetVal = UFix(0,2));
when (io.mem.resp_val) {
refill_count <== refill_count + UFix(1);
@ -119,12 +107,11 @@ class rocketICacheDM(lines: Int) extends Component {
tag_array.io.d := r_cpu_req_ppn;
tag_array.io.we := tag_we;
tag_array.io.bweb := ~Bits(0,tagbits);
tag_array.io.ce := (state === s_ready) && io.cpu.req_val;
tag_array.io.ce := (io.cpu.req_val && io.cpu.req_rdy);
val tag_rdata = tag_array.io.q;
// valid bit array
val vb_array = Reg(resetVal = Bits(0, lines));
// val vb_rdata = Reg(vb_array(io.cpu.req_addr(indexmsb, indexlsb)));
when (tag_we) {
vb_array <== vb_array.bitSet(r_cpu_req_idx(PGIDX_BITS-1,offsetbits).toUFix, UFix(1,1));
}
@ -140,7 +127,6 @@ class rocketICacheDM(lines: Int) extends Component {
data_array.io.d := io.mem.resp_data;
data_array.io.we := io.mem.resp_val;
data_array.io.bweb := ~Bits(0,128);
// data_array.io.ce := Bool(true); // FIXME
data_array.io.ce := (io.cpu.req_rdy && io.cpu.req_val) || (state === s_resolve_miss);
val data_array_rdata = data_array.io.q;
@ -156,7 +142,6 @@ class rocketICacheDM(lines: Int) extends Component {
io.mem.req_val := (state === s_request);
io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
// Cat(r_cpu_req_addr(tagmsb, indexlsb), Bits(0,2)).toUFix;
// control state machine
switch (state) {