code cleanup/parameterization
This commit is contained in:
Andrew Waterman
parent
a87ad06780
commit
218f63e66e
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@ -10,15 +10,15 @@ class ioMem() extends Bundle
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val req_rdy = Bool('input);
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val req_rw = Bool('output);
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val req_addr = UFix(PADDR_BITS, 'output);
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val req_wdata = Bits(128, 'output);
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val req_tag = Bits(4, 'output);
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val req_wdata = Bits(MEM_DATA_BITS, 'output);
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val req_tag = Bits(MEM_TAG_BITS, 'output);
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val resp_val = Bool('input);
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val resp_tag = Bits(4, 'input);
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val resp_data = Bits(128, 'input);
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val resp_tag = Bits(MEM_TAG_BITS, 'input);
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val resp_data = Bits(MEM_DATA_BITS, 'input);
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}
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class ioArbiter extends Bundle() {
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class ioMemArbiter extends Bundle() {
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val mem = new ioMem();
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val dcache = new ioDcache();
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// val icache = new ioIcache();
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@ -26,7 +26,7 @@ class ioArbiter extends Bundle() {
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}
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class rocketMemArbiter extends Component {
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val io = new ioArbiter();
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val io = new ioMemArbiter();
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// *****************************
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// Interface to memory
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@ -41,11 +41,8 @@ class rocketMemArbiter extends Component {
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// Give priority to Icache
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io.mem.req_addr := Mux(io.icache.req_val,io.icache.req_addr,io.dcache.req_addr);
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// high bit of tag=0 for I$, tag=0 for D$
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// io.mem.req_tag := Mux(io.icache.req_val,Bits(0,4),Bits(1,4));
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io.mem.req_tag := Mux(io.icache.req_val,
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Cat(Bits(0,1), io.icache.req_tag),
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Cat(Bits(1,1), io.dcache.req_tag));
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// low bit of tag=0 for I$, 1 for D$
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io.mem.req_tag := Cat(Mux(io.icache.req_val, io.icache.req_tag, io.dcache.req_tag), !io.icache.req_val)
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// Just pass through write data (only D$ will write)
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io.mem.req_wdata := io.dcache.req_wdata;
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@ -59,15 +56,15 @@ class rocketMemArbiter extends Component {
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io.dcache.req_rdy := io.mem.req_rdy && !io.icache.req_val;
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// Response will only be valid for D$ or I$ not both because of tag bits
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io.icache.resp_val := io.mem.resp_val && !io.mem.resp_tag(3).toBool;
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io.dcache.resp_val := io.mem.resp_val && io.mem.resp_tag(3).toBool;
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io.icache.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
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io.dcache.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
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// Feed through data to both
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io.icache.resp_data := io.mem.resp_data;
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io.dcache.resp_data := io.mem.resp_data;
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io.icache.resp_tag := io.mem.resp_tag(2,0);
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// io.dcache.resp_tag := io.mem.resp_tag(2,0);
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io.icache.resp_tag := io.mem.resp_tag >> UFix(1)
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io.dcache.resp_tag := io.mem.resp_tag >> UFix(1)
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}
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@ -1,6 +1,7 @@
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package Top {
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import Chisel._
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import scala.math._
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object Constants
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{
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@ -125,10 +126,12 @@ object Constants
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val M_X = UFix(0, 4);
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val M_XRD = Bits("b0000", 4); // int load
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val M_XWR = Bits("b0001", 4); // int store
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val M_FRD = Bits("b0010", 4); // fp load
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val M_FWR = Bits("b0011", 4); // fp store
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val M_FLA = Bits("b0100", 4); // flush cache
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val M_PFR = Bits("b0010", 4); // prefetch with intent to read
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val M_PFW = Bits("b0011", 4); // prefetch with intent to write
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val M_FLA = Bits("b0100", 4); // write back and invlaidate all lines
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val M_PRD = Bits("b0101", 4); // PTW load
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val M_INV = Bits("b0110", 4); // write back and invalidate line
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val M_CLN = Bits("b0111", 4); // write back line
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val M_XA_ADD = Bits("b1000", 4);
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val M_XA_SWAP = Bits("b1001", 4);
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val M_XA_AND = Bits("b1010", 4);
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@ -183,6 +186,23 @@ object Constants
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val VPN_BITS = VADDR_BITS-PGIDX_BITS;
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val ASID_BITS = 7;
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val PERM_BITS = 6;
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// rocketNBDCacheDM parameters
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val CPU_DATA_BITS = 64;
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val CPU_TAG_BITS = 5;
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val OFFSET_BITS = 6; // log2(cache line size in bytes)
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val NMSHR = 2; // number of primary misses
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val NRPQ = 16; // number of secondary misses
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val NSDQ = 10; // number of secondary stores/AMOs
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val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
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val IDX_BITS = PGIDX_BITS - OFFSET_BITS;
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// external memory interface
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val IMEM_TAG_BITS = 1;
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val DMEM_TAG_BITS = ceil(log(NMSHR)/log(2)).toInt;
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val MEM_TAG_BITS = 1 + max(IMEM_TAG_BITS, DMEM_TAG_BITS);
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val MEM_DATA_BITS = 128;
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val REFILL_CYCLES = (1 << OFFSET_BITS)*8/MEM_DATA_BITS;
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val DTLB_ENTRIES = 8;
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val ITLB_ENTRIES = 8;
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@ -27,13 +27,13 @@ class ioDmem(view: List[String] = null) extends Bundle(view) {
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// interface between D$ and next level in memory hierarchy
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class ioDcache(view: List[String] = null) extends Bundle(view) {
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val req_addr = UFix(PADDR_BITS, 'input);
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val req_tag = UFix(3, 'input);
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val req_tag = UFix(DMEM_TAG_BITS, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val req_wdata = Bits(128, 'input);
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val req_rw = Bool('input);
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val resp_data = Bits(128, 'output);
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// val resp_tag = Bits(3, 'output);
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val resp_tag = Bits(DMEM_TAG_BITS, 'output);
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val resp_val = Bool('output);
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}
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@ -24,7 +24,7 @@ class ioIcache(view: List[String] = null) extends Bundle (view)
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val req_addr = UFix(PADDR_BITS, 'input);
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val req_val = Bool('input);
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val req_rdy = Bool('output);
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val resp_data = Bits(128, 'output);
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val resp_data = Bits(MEM_DATA_BITS, 'output);
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val resp_val = Bool('output);
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}
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@ -50,8 +50,9 @@ class rocketICacheDM(lines: Int) extends Component {
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val indexmsb = taglsb-1;
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val indexlsb = offsetbits;
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val offsetmsb = indexlsb-1;
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val offsetlsb = 2;
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val databits = 32;
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val offsetlsb = ceil(log(databits/8)/log(2)).toInt;
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val rf_cnt_bits = ceil(log(REFILL_CYCLES)/log(2)).toInt;
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val s_reset :: s_ready :: s_request :: s_refill_wait :: s_refill :: s_resolve_miss :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_reset);
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@ -74,7 +75,7 @@ class rocketICacheDM(lines: Int) extends Component {
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}
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// refill counter
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val refill_count = Reg(resetVal = UFix(0,2));
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val refill_count = Reg(resetVal = UFix(0, rf_cnt_bits));
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when (io.mem.resp_val) {
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refill_count <== refill_count + UFix(1);
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}
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@ -104,7 +105,7 @@ class rocketICacheDM(lines: Int) extends Component {
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val data_addr =
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Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(PGIDX_BITS-1, offsetbits), refill_count),
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io.cpu.req_idx(PGIDX_BITS-1, offsetmsb-1)).toUFix;
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val data_array = Mem4(lines*4, io.mem.resp_data);
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val data_array = Mem4(lines*REFILL_CYCLES, io.mem.resp_data);
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data_array.setReadLatency(SRAM_READ_LATENCY);
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// data_array.setTarget('inst);
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val data_array_rdata = data_array.rw(data_addr, io.mem.resp_data, io.mem.resp_val);
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@ -112,14 +113,14 @@ class rocketICacheDM(lines: Int) extends Component {
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// output signals
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io.cpu.resp_val := !io.cpu.itlb_miss && (state === s_ready) && r_cpu_req_val && tag_valid && tag_match;
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io.cpu.req_rdy := !io.cpu.itlb_miss && (state === s_ready) && (!r_cpu_req_val || (tag_valid && tag_match));
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io.cpu.resp_data :=
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MuxLookup(r_cpu_req_idx(offsetmsb-2, offsetlsb).toUFix, data_array_rdata(127, 96),
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Array(UFix(2) -> data_array_rdata(95,64),
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UFix(1) -> data_array_rdata(63,32),
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UFix(0) -> data_array_rdata(31,0)));
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val word_mux = (new MuxN(REFILL_CYCLES)) { Bits(width = databits) }
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word_mux.io.sel := r_cpu_req_idx(offsetmsb - rf_cnt_bits, offsetlsb).toUFix
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for (i <- 0 to MEM_DATA_BITS/databits-1) { word_mux.io.in(i) := data_array_rdata((i+1)*databits-1, i*databits) }
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io.cpu.resp_data := word_mux.io.out
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io.mem.req_val := (state === s_request);
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0,2)).toUFix;
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io.mem.req_addr := Cat(r_cpu_req_ppn, r_cpu_req_idx(PGIDX_BITS-1, offsetbits), Bits(0, rf_cnt_bits)).toUFix;
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// control state machine
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switch (state) {
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@ -146,7 +147,7 @@ class rocketICacheDM(lines: Int) extends Component {
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}
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}
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is (s_refill) {
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when (io.mem.resp_val && (refill_count === UFix(3,2))) {
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when (io.mem.resp_val && (~refill_count === UFix(0))) {
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state <== s_resolve_miss;
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}
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}
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@ -3,17 +3,17 @@ package Top {
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import Chisel._;
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import Node._;
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import Constants._;
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import queues._;
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import scala.math._;
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class ioIPrefetcherMem(view: List[String] = null) extends Bundle (view)
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{
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val req_addr = UFix(PADDR_BITS, 'output);
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val req_val = Bool('output);
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val req_rdy = Bool('input);
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val req_tag = Bits(3, 'output);
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val resp_data = Bits(128, 'input);
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val req_tag = Bits(IMEM_TAG_BITS, 'output);
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val resp_data = Bits(MEM_DATA_BITS, 'input);
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val resp_val = Bool('input);
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val resp_tag = Bits(3, 'input);
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val resp_tag = Bits(IMEM_TAG_BITS, 'input);
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}
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class ioIPrefetcher extends Bundle() {
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@ -23,14 +23,14 @@ class ioIPrefetcher extends Bundle() {
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class rocketIPrefetcher extends Component() {
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val io = new ioIPrefetcher();
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val pdq = (new queueSimplePF(4)) { Bits(width = 128) };
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val pdq = (new queueSimplePF(REFILL_CYCLES)) { Bits(width = MEM_DATA_BITS) };
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val s_invalid :: s_valid :: s_refilling :: s_req_wait :: s_resp_wait :: s_bad_resp_wait :: Nil = Enum(6) { UFix() };
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val state = Reg(resetVal = s_invalid);
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val demand_miss = io.icache.req_val & io.icache.req_rdy;
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val prefetch_addr = Reg(resetVal = UFix(0,32));
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when (demand_miss) { prefetch_addr <== io.icache.req_addr + UFix(4); }
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val prefetch_addr = Reg() { UFix(width = PADDR_BITS) };
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when (demand_miss) { prefetch_addr <== io.icache.req_addr + UFix(REFILL_CYCLES); }
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val addr_match = (prefetch_addr === io.icache.req_addr);
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val hit = (state != s_invalid) & (state != s_req_wait) & addr_match;
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@ -40,29 +40,29 @@ class rocketIPrefetcher extends Component() {
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val ip_mem_resp_val = io.mem.resp_val && io.mem.resp_tag(0).toBool;
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io.mem.req_val := io.icache.req_val & ~hit | (state === s_req_wait);
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io.mem.req_tag := Cat(Bits(0,2), !(io.icache.req_val && !hit));
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io.mem.req_tag := !(io.icache.req_val && !hit);
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io.mem.req_addr := Mux(io.mem.req_tag(0).toBool, prefetch_addr, io.icache.req_addr);
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val pdq_reset = Reg(resetVal = Bool(true));
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pdq_reset <== demand_miss & ~hit | (state === s_bad_resp_wait);
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val fill_cnt = Reg(resetVal = UFix(0,2));
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when (ip_mem_resp_val.toBool) { fill_cnt <== fill_cnt + UFix(1,1); }
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val fill_done = (fill_cnt === UFix(3,2)) & ip_mem_resp_val;
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val fill_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (ip_mem_resp_val.toBool) { fill_cnt <== fill_cnt + UFix(1); }
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val fill_done = (~fill_cnt === UFix(0)) & ip_mem_resp_val;
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val forward = Reg(resetVal = Bool(false));
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val forward_cnt = Reg(resetVal = UFix(0,2));
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when (forward & pdq.io.deq_val) { forward_cnt <== forward_cnt + UFix(1,1); }
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val forward_done = (forward_cnt === UFix(3,2)) & pdq.io.deq_val;
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val forward_cnt = Reg(resetVal = UFix(0, ceil(log(REFILL_CYCLES)/log(2)).toInt));
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when (forward & pdq.io.deq.valid) { forward_cnt <== forward_cnt + UFix(1); }
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val forward_done = (~forward_cnt === UFix(0)) & pdq.io.deq.valid;
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forward <== (demand_miss & hit | forward & ~forward_done);
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io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq_val);
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io.icache.resp_data := Mux(forward, pdq.io.deq_bits, io.mem.resp_data);
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io.icache.resp_val := (io.mem.resp_val && !io.mem.resp_tag(0).toBool) || (forward && pdq.io.deq.valid);
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io.icache.resp_data := Mux(forward, pdq.io.deq.bits, io.mem.resp_data);
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pdq.io.q_reset := pdq_reset;
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pdq.io.enq_bits := io.mem.resp_data;
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pdq.io.enq_val := ip_mem_resp_val.toBool;
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pdq.io.deq_rdy := forward;
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pdq.io.enq.bits := io.mem.resp_data;
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pdq.io.enq.valid := ip_mem_resp_val.toBool;
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pdq.io.deq.ready := forward;
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switch (state) {
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is (s_invalid) {
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@ -1,4 +1,4 @@
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package queues
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package Top
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{
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import Chisel._
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@ -81,15 +81,11 @@ class queueCtrl(entries: Int) extends Component
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full <== full_next;
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}
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class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle()
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class ioQueueSimplePF[T <: Data]()(data: => T) extends Bundle
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{
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val q_reset = Bool('input);
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val enq_val = Bool('input);
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val enq_rdy = Bool('output);
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val deq_val = Bool('output);
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val deq_rdy = Bool('input);
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val enq_bits = data.asInput;
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val deq_bits = data.asOutput;
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val q_reset = Bool('input);
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val enq = new ioDecoupled()(data)
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val deq = new ioDecoupled()(data).flip
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}
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class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
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@ -97,12 +93,12 @@ class queueSimplePF[T <: Data](entries: Int)(data: => T) extends Component
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override val io = new ioQueueSimplePF()(data);
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val ctrl = new queueCtrl(entries);
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ctrl.io.q_reset ^^ io.q_reset;
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ctrl.io.deq_val ^^ io.deq_val;
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ctrl.io.enq_rdy ^^ io.enq_rdy;
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ctrl.io.enq_val ^^ io.enq_val;
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ctrl.io.deq_rdy ^^ io.deq_rdy;
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val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq_bits);
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ram.read(ctrl.io.raddr) ^^ io.deq_bits;
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ctrl.io.deq_val ^^ io.deq.valid;
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ctrl.io.enq_rdy ^^ io.enq.ready;
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ctrl.io.enq_val ^^ io.enq.valid;
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ctrl.io.deq_rdy ^^ io.deq.ready;
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val ram = Mem(entries, ctrl.io.wen, ctrl.io.waddr, io.enq.bits);
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ram.read(ctrl.io.raddr) ^^ io.deq.bits;
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}
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// TODO: SHOULD USE INHERITANCE BUT BREAKS INTROSPECTION CODE
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@ -5,6 +5,79 @@ import Chisel._
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import Node._;
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import scala.math._;
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class MuxN[T <: Data](n: Int)(data: => T) extends Component {
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val io = new Bundle {
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val sel = Bits(width = ceil(log(n)/log(2)).toInt)
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val in = Vec(n) { data }.asInput()
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val out = data.asOutput()
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}
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val out = Vec(n) { Wire() { data } }
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out(0) <== io.in(0)
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for (i <- 1 to n-1) {
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out(i) <== Mux(io.sel === UFix(i), io.in(i), out(i-1))
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}
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out(n-1) ^^ io.out
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}
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class Mux1H(n: Int, w: Int) extends Component
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{
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val io = new Bundle {
|
||||
val sel = Vec(n) { Bool(dir = 'input) }
|
||||
val in = Vec(n) { Bits(width = w, dir = 'input) }
|
||||
val out = Bits(width = w, dir = 'output)
|
||||
}
|
||||
|
||||
if (n > 1) {
|
||||
val out = Vec(n) { Wire() { Bits(width = w) } }
|
||||
out(0) <== io.in(0) & Fill(w, io.sel(0))
|
||||
for (i <- 1 to n-1) {
|
||||
out(i) <== out(i-1) | (io.in(i) & Fill(w, io.sel(i)))
|
||||
}
|
||||
|
||||
io.out := out(n-1)
|
||||
} else {
|
||||
io.out := io.in(0)
|
||||
}
|
||||
}
|
||||
|
||||
class ioDecoupled[T <: Data]()(data: => T) extends Bundle
|
||||
{
|
||||
val valid = Bool('input)
|
||||
val ready = Bool('output)
|
||||
val bits = data.asInput
|
||||
}
|
||||
|
||||
class ioArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
|
||||
val in = Vec(n) { (new ioDecoupled()) { data } }
|
||||
val out = (new ioDecoupled()) { data }.flip()
|
||||
}
|
||||
|
||||
class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
|
||||
val io = new ioArbiter(n)(data)
|
||||
val dout = Vec(n) { Wire() { data } }
|
||||
val vout = Wire { Bool() }
|
||||
|
||||
io.in(0).ready := io.out.ready
|
||||
for (i <- 1 to n-1) {
|
||||
io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
|
||||
}
|
||||
|
||||
dout(n-1) <== io.in(n-1).bits
|
||||
for (i <- n-2 to 0) {
|
||||
dout(i) <== Mux(io.in(i).valid, io.in(i).bits, dout(i+1))
|
||||
}
|
||||
|
||||
for (i <- 0 to n-2) {
|
||||
when (io.in(i).valid) { vout <== Bool(true) }
|
||||
}
|
||||
vout <== io.in(n-1).valid
|
||||
|
||||
vout ^^ io.out.valid
|
||||
dout(0) ^^ io.out.bits
|
||||
}
|
||||
|
||||
class ioPriorityDecoder(in_width: Int, out_width: Int) extends Bundle
|
||||
{
|
||||
val in = UFix(in_width, 'input);
|
||||
|
|
@ -49,4 +122,4 @@ class priorityEncoder(width: Int) extends Component
|
|||
io.out := l_out;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue