Henry Cook
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5d2a470215
|
all rocket-specific arbiters in one file and refactored traits slightly
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2012-10-15 16:05:32 -07:00 |
|
Henry Cook
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
|
Henry Cook
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dfdfddebe8
|
constants as traits
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2012-10-07 22:20:03 -07:00 |
|
Huy Vo
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e909093f37
|
factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
|
Huy Vo
|
d9cb96c0ae
|
factored out common stuff to ChiselUtil
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2012-09-27 22:53:34 -07:00 |
|
Andrew Waterman
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b94e6915ab
|
refactor IPIs; use new tohost/fromhost protocol
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2012-08-03 19:00:34 -07:00 |
|
Andrew Waterman
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9c50621a19
|
remove chip-specific uncore gunk
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2012-07-26 03:26:52 -07:00 |
|
Andrew Waterman
|
177dbdadd9
|
merge HTIF port and backup memory port
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2012-07-25 00:18:02 -07:00 |
|
Yunsup Lee
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309193dd07
|
change llc size
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2012-07-24 14:10:29 -07:00 |
|
Yunsup Lee
|
f4e3e72ad1
|
hoist HTIF_WIDTH out to consts
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2012-07-23 17:30:04 -07:00 |
|
Yunsup Lee
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379f021359
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change ioHTIF interface between the tile/uncore boundary to cope with asynchrony
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2012-07-22 18:26:02 -07:00 |
|
Yunsup Lee
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c892950bf1
|
hoist out uncore as its own component
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2012-07-22 17:48:17 -07:00 |
|
Andrew Waterman
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f42c6afed2
|
decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
|
2012-07-17 22:55:40 -07:00 |
|
Andrew Waterman
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f645fb4dd7
|
add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Andrew Waterman
|
943b6d0616
|
remove debug println
|
2012-06-06 02:48:48 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
181b20d69c
|
working vec unit with pvfb
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2012-05-24 10:38:14 -07:00 |
|
Andrew Waterman
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171c87002e
|
reduce HTIF clock divider for now
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2012-05-03 04:21:11 -07:00 |
|
Andrew Waterman
|
4cfa6cd9a8
|
force Top.main's return type to Unit
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2012-05-01 19:55:16 -07:00 |
|
Henry Cook
|
fef58f1b3a
|
Policy determined by constants. MSI policy added.
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2012-04-11 17:56:59 -07:00 |
|
Andrew Waterman
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c0ec3794bf
|
coherence mostly works now
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2012-04-10 02:22:45 -07:00 |
|
Henry Cook
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3cdd166153
|
Refactored coherence as member rather than trait. MI and MEI protocols.
|
2012-04-10 00:09:58 -07:00 |
|
Andrew Waterman
|
6bda8674bd
|
no dessert tonight :(
|
2012-03-26 23:50:09 -07:00 |
|
Andrew Waterman
|
ef505de017
|
reduce HTIF width
|
2012-03-25 23:49:45 -07:00 |
|
Andrew Waterman
|
31f0b600fd
|
add dessert
|
2012-03-25 23:03:20 -07:00 |
|
Andrew Waterman
|
f62a02ab54
|
remove dumb stuff in top.scala
|
2012-03-25 21:30:01 -07:00 |
|
Andrew Waterman
|
7fa93da4f5
|
add backup memory port (disabled for now)
|
2012-03-25 15:49:32 -07:00 |
|
Andrew Waterman
|
86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
2b0bc8df2b
|
use divided clk for htif. UDPATE YOUR FESVR
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
|
2012-03-15 18:36:51 -07:00 |
|
Yunsup Lee
|
ba566f246e
|
change icache parameters
|
2012-03-15 15:35:12 -07:00 |
|
Andrew Waterman
|
7dde7099d2
|
use broadcast hub and coherent HTIF
|
2012-03-14 16:44:35 -07:00 |
|
Andrew Waterman
|
b0f798962c
|
add probe unit
|
2012-03-13 16:43:51 -07:00 |
|
Yunsup Lee
|
1aa4b0e93d
|
going back to null coherence hub
|
2012-03-10 20:16:20 -08:00 |
|
Andrew Waterman
|
8ffdac9526
|
fix D$ store-upgrade bug
loads to the same address as stores that cause an upgrade
could return the old value
|
2012-03-10 15:50:10 -08:00 |
|
Andrew Waterman
|
6e16b04ada
|
implement transaction finish messages
|
2012-03-06 15:48:08 -08:00 |
|
Andrew Waterman
|
5f12990dfb
|
support memory transaction aborts
|
2012-03-06 00:35:02 -08:00 |
|
Andrew Waterman
|
28cacd953f
|
D$ cleanup - merge ReplayUnit and MSHRFile
|
2012-03-01 19:30:56 -08:00 |
|
Andrew Waterman
|
52101373e0
|
clean up D$ store data unit
|
2012-03-01 19:20:00 -08:00 |
|
Henry Cook
|
9d7707a0a2
|
Made xact_rep an ioValid, removed has_data member
|
2012-03-01 18:24:21 -08:00 |
|
Henry Cook
|
c6162ac743
|
Unified hub ios. Fixed some hub elaboration errors.
|
2012-03-01 01:20:57 -08:00 |
|
Andrew Waterman
|
b9ec69f8f5
|
add new Queue singleton
|
2012-02-29 14:21:42 -08:00 |
|
Andrew Waterman
|
012da6002e
|
replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
|
2012-02-29 03:10:47 -08:00 |
|
Andrew Waterman
|
c99f6bbeb7
|
separate memory request command and data
also, merge some VLSI/C++ test harness functionality
|
2012-02-28 19:06:23 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Andrew Waterman
|
7c929afe2b
|
HTIF now controls CPU reset
|
2012-02-22 19:30:03 -08:00 |
|
Andrew Waterman
|
9a80adef50
|
only instantiate VI$ if HAVE_VEC
|
2012-02-21 15:53:19 -08:00 |
|
Andrew Waterman
|
6135615104
|
unify cache backend interfaces; generify arbiter
|
2012-02-20 00:51:48 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Andrew Waterman
|
9af86633d7
|
invalidate I$ prefetcher when invalidating I$
|
2012-02-17 17:56:01 -08:00 |
|
Henry Cook
|
d46e59a16d
|
Abstract base nbcache class
|
2012-02-16 12:34:51 -08:00 |
|