012da6002e
work in progress towards coherent HTIF. for now, requests are incoherently passed through a null coherence hub.
74 lines
2.3 KiB
Scala
74 lines
2.3 KiB
Scala
package rocket
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import Chisel._
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import Node._;
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import Constants._;
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new ioDebug();
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val host = new ioHost(htif_width);
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val mem = new ioMem
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}
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class Top() extends Component {
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val htif_width = 16
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val io = new ioTop(htif_width);
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val htif = new rocketHTIF(htif_width, 1)
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val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset);
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache_pf = new rocketIPrefetcher();
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val dcache = new HellaCacheUniproc();
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val arbiter = new rocketMemArbiter(3 + (if (HAVE_VEC) 1 else 0));
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(2) <> htif.io.mem
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val hub = new CoherenceHubNull
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// connect tile to hub (figure out how to do this more compactly)
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val xact_init_q = (new queue(2)) { new TransactionInit }
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xact_init_q.io.enq <> arbiter.io.mem.xact_init
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xact_init_q.io.deq <> hub.io.tile.xact_init
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val xact_init_data_q = (new queue(2)) { new TransactionInitData }
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xact_init_data_q.io.enq <> arbiter.io.mem.xact_init_data
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xact_init_data_q.io.deq <> hub.io.tile.xact_init_data
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val xact_rep_q = (new queue(1, pipe = true)) { new TransactionReply }
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xact_rep_q.io.enq <> hub.io.tile.xact_rep
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xact_rep_q.io.deq <> arbiter.io.mem.xact_rep
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// connect hub to memory
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val mem_req_q = (new queue(2)) { new MemReqCmd }
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mem_req_q.io.enq <> hub.io.mem.req_cmd
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mem_req_q.io.deq <> io.mem.req_cmd
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val mem_req_data_q = (new queue(2)) { new MemData }
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mem_req_data_q.io.enq <> hub.io.mem.req_data
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mem_req_data_q.io.deq <> io.mem.req_data
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hub.io.mem.resp.valid := Reg(io.mem.resp.valid, resetVal = Bool(false))
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hub.io.mem.resp.bits := Reg(io.mem.resp.bits)
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if (HAVE_VEC)
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{
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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arbiter.io.requestor(3) <> vicache.io.mem
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cpu.io.vimem <> vicache.io.cpu;
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}
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htif.io.host <> io.host
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cpu.io.host <> htif.io.cpu(0);
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cpu.io.debug <> io.debug;
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icache_pf.io.invalidate := cpu.io.imem.invalidate
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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}
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object top_main {
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def main(args: Array[String]) = {
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chiselMain(args, () => new Top());
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}
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}
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