riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

change ioHTIF interface between the tile/uncore boundary to cope with asynchrony

Browse Source
This commit is contained in:
Yunsup Lee 2012-07-22 18:26:02 -07:00
parent c892950bf1
commit 379f021359
2 changed files with 10 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/htif.scala
View File

@ -27,7 +27,7 @@ class ioHTIF extends Bundle
val reset = Bool(INPUT)
val debug = new ioDebug
val pcr_req = (new FIFOIO) { new PCRReq }.flip
val pcr_rep = (new PipeIO) { Bits(width = 64) }
val pcr_rep = (new FIFOIO) { Bits(width = 64) }
val ipi = (new FIFOIO) { Bits(width = log2Up(NTILES)) }
}
@ -220,6 +220,8 @@ class rocketHTIF(w: Int, ncores: Int, co: CoherencePolicyWithUncached) extends C
my_reset := pcr_wdata(0)
}
}
cpu.pcr_rep.ready := Bool(true)
when (cpu.pcr_rep.valid) {
pcr_done := Bool(true)
rdata := cpu.pcr_rep.bits

9
rocket/src/main/scala/top.scala
View File

@ -107,7 +107,13 @@ class Top extends Component
val hl = uncore.io.htif(i)
val tl = uncore.io.tiles(i)
val tile = new Tile(co, resetSignal = hl.reset)
tile.io.host <> hl
tile.io.host.reset := Reg(Reg(hl.reset))
tile.io.host.pcr_req <> Queue(hl.pcr_req)
hl.pcr_rep <> Queue(tile.io.host.pcr_rep)
hl.ipi <> Queue(tile.io.host.ipi)
error_mode = error_mode || Reg(tile.io.host.debug.error_mode)
tl.xact_init <> Queue(tile.io.tilelink.xact_init)
tl.xact_init_data <> Queue(tile.io.tilelink.xact_init_data)
tile.io.tilelink.xact_abort <> Queue(tl.xact_abort)
@ -117,7 +123,6 @@ class Top extends Component
tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
tl.incoherent := hl.reset
error_mode = error_mode || tile.io.host.debug.error_mode
}
io.debug.error_mode := error_mode
}