riscv/rocket-chip
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working vec unit with pvfb

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This commit is contained in:
Huy Vo 2012-05-18 12:43:32 -07:00
parent faee45bf4c
commit 181b20d69c
3 changed files with 32 additions and 3 deletions
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2
rocket/src/main/scala/consts.scala
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@ -10,6 +10,8 @@ object Constants
val HAVE_FPU = true
val HAVE_VEC = true
val MAX_THREADS = hwacha.Constants.NUM_PVFB * hwacha.Constants.WIDTH_PVFB / hwacha.Constants.SZ_BANK
val MEM_BACKUP_WIDTH = 16
val BR_X = Bits("b????", 4)

7
rocket/src/main/scala/dpath_vec.scala
View File

@ -46,7 +46,9 @@ class rocketDpathVec extends Component
val nfregs = Mux(nfregs_stage(5), Bits(32), nfregs_stage) + UFix(0,7)
val nregs = nxregs + nfregs
val uts_per_bank = MuxLookup(
//val uts_per_bank = UFix(4,9)
val nreg_mod_bank = MuxLookup(
nregs, UFix(4,9), Array(
UFix(0,7) -> UFix(256,9),
UFix(1,7) -> UFix(256,9),
@ -103,6 +105,9 @@ class rocketDpathVec extends Component
UFix(52,7) -> UFix(5,9)
))
val uts_per_bank = Mux(nreg_mod_bank > UFix(MAX_THREADS,9), UFix(MAX_THREADS, 9), nreg_mod_bank)
val reg_hwvl = Reg(resetVal = UFix(32, 12))
val reg_appvl0 = Reg(resetVal = Bool(true))
val hwvl_vcfg = (uts_per_bank * io.vecbankcnt)(11,0)

26
rocket/src/main/scala/top.scala
View File

@ -81,7 +81,29 @@ class Top extends Component
}
object top_main {
def main(args: Array[String]): Unit = {
chiselMain(args.drop(1), () => Class.forName(args(0)).newInstance.asInstanceOf[Component])
def main(args: Array[String]): Unit = {
val design_args = args.slice(5, 10)
var i = 0
while (i < design_args.length) {
val arg = design_args(i)
arg match {
case "--NUM_PVFB" => {
hwacha.Constants.NUM_PVFB = design_args(i+1).toInt
i += 1
}
case "--WIDTH_PVFB" => {
hwacha.Constants.WIDTH_PVFB = design_args(i+1).toInt
hwacha.Constants.DEPTH_PVFB = design_args(i+1).toInt
i += 1
}
case "--CG" => {
hwacha.Constants.coarseGrained = true
}
case any => println("UNKNOWN: " + arg)
}
println(arg)
i += 1
}
chiselMain(args.slice(1,5), () => Class.forName(args(0)).newInstance.asInstanceOf[Component])
}
}