69 lines
2.0 KiB
Scala
69 lines
2.0 KiB
Scala
package rocket
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import Chisel._
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import Node._;
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import Constants._;
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new ioDebug();
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val host = new ioHost(htif_width);
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val mem = new ioMem
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}
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class Top() extends Component {
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val htif_width = 16
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val io = new ioTop(htif_width);
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val htif = new rocketHTIF(htif_width, 1)
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val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset);
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache_pf = new rocketIPrefetcher();
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val dcache = new HellaCacheUniproc();
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val arbiter = new rocketMemArbiter(3 + (if (HAVE_VEC) 1 else 0));
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arbiter.io.requestor(0) <> dcache.io.mem
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arbiter.io.requestor(1) <> icache_pf.io.mem
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arbiter.io.requestor(2) <> htif.io.mem
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val hub = new CoherenceHubNull
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// connect tile to hub
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hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
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arbiter.io.mem.xact_abort <> Queue(hub.io.tiles(0).xact_abort)
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arbiter.io.mem.xact_rep <> Pipe(hub.io.tiles(0).xact_rep)
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hub.io.tiles(0).xact_finish <> Queue(arbiter.io.mem.xact_finish)
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// connect hub to memory
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io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
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io.mem.req_data <> Queue(hub.io.mem.req_data)
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hub.io.mem.resp <> Pipe(io.mem.resp)
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// temporary HTIF data connection
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val data_arb = (new Arbiter(2)) { new TransactionInitData }
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data_arb.io.in(0) <> Queue(dcache.io.mem.xact_init_data)
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data_arb.io.in(1) <> Queue(htif.io.mem.xact_init_data)
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hub.io.tiles(0).xact_init_data <> data_arb.io.out
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if (HAVE_VEC)
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{
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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arbiter.io.requestor(3) <> vicache.io.mem
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cpu.io.vimem <> vicache.io.cpu;
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}
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htif.io.host <> io.host
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cpu.io.host <> htif.io.cpu(0);
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cpu.io.debug <> io.debug;
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icache_pf.io.invalidate := cpu.io.imem.invalidate
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icache.io.mem <> icache_pf.io.icache;
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cpu.io.imem <> icache.io.cpu;
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cpu.io.dmem <> dcache.io.cpu;
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}
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object top_main {
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def main(args: Array[String]) = {
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chiselMain(args, () => new Top());
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}
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}
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