factored out common stuff to ChiselUtil
This commit is contained in:
Huy Vo
parent
667b4ee858
commit
d9cb96c0ae
@ -3,99 +3,6 @@ package rocket
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import Chisel._
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import Node._;
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class ioQueue[T <: Data](entries: Int)(data: => T) extends Bundle
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{
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val enq = new FIFOIO()(data).flip
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val deq = new FIFOIO()(data)
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val count = UFix(OUTPUT, log2Up(entries+1))
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}
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class Queue[T <: Data](val entries: Int, pipe: Boolean = false, flow: Boolean = false, resetSignal: Bool = null)(data: => T) extends Component(resetSignal)
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{
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val io = new ioQueue(entries)(data)
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val do_flow = Bool()
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val do_enq = io.enq.ready && io.enq.valid && !do_flow
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val do_deq = io.deq.ready && io.deq.valid && !do_flow
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var enq_ptr = UFix(0)
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var deq_ptr = UFix(0)
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if (entries > 1)
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{
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enq_ptr = Counter(do_enq, entries)._1
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deq_ptr = Counter(do_deq, entries)._1
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}
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val maybe_full = Reg(resetVal = Bool(false))
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when (do_enq != do_deq) {
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maybe_full := do_enq
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}
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val ram = Mem(entries) { data }
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when (do_enq) { ram(enq_ptr) := io.enq.bits }
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val ptr_match = enq_ptr === deq_ptr
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val empty = ptr_match && !maybe_full
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val full = ptr_match && maybe_full
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val maybe_flow = Bool(flow) && empty
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do_flow := maybe_flow && io.deq.ready
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io.deq.valid := !empty || Bool(flow) && io.enq.valid
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io.enq.ready := !full || Bool(pipe) && io.deq.ready
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io.deq.bits := Mux(maybe_flow, io.enq.bits, ram(deq_ptr))
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val ptr_diff = enq_ptr - deq_ptr
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if (isPow2(entries))
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io.count := Cat(maybe_full && ptr_match, ptr_diff).toUFix
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else
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io.count := Mux(ptr_match, Mux(maybe_full, UFix(entries), UFix(0)), Mux(deq_ptr > enq_ptr, UFix(entries) + ptr_diff, ptr_diff))
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}
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object Queue
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{
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def apply[T <: Data](enq: FIFOIO[T], entries: Int = 2, pipe: Boolean = false) = {
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val q = (new Queue(entries, pipe)) { enq.bits.clone }
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q.io.enq.valid := enq.valid // not using <> so that override is allowed
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q.io.enq.bits := enq.bits
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enq.ready := q.io.enq.ready
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q.io.deq
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}
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}
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class Pipe[T <: Data](latency: Int = 1)(data: => T) extends Component
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{
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val io = new Bundle {
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val enq = new PipeIO()(data).flip
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val deq = new PipeIO()(data)
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}
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var bits: T = io.enq.bits
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var valid: Bool = io.enq.valid
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for (i <- 0 until latency) {
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val reg_bits = Reg() { io.enq.bits.clone }
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val reg_valid = Reg(valid, resetVal = Bool(false))
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when (valid) { reg_bits := bits }
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valid = reg_valid
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bits = reg_bits
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}
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io.deq.valid := valid
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io.deq.bits := bits
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}
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object Pipe
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{
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def apply[T <: Data](enqValid: Bool, enqBits: T, latency: Int): PipeIO[T] = {
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val q = (new Pipe(latency)) { enqBits.clone }
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q.io.enq.valid := enqValid
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q.io.enq.bits := enqBits
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q.io.deq
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}
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def apply[T <: Data](enqValid: Bool, enqBits: T): PipeIO[T] = apply(enqValid, enqBits, 1)
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def apply[T <: Data](enq: PipeIO[T], latency: Int = 1): PipeIO[T] = apply(enq.valid, enq.bits, latency)
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}
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class SkidBuffer[T <: Data](resetSignal: Bool = null)(data: => T) extends Component(resetSignal)
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{
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val io = new Bundle {
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@ -3,7 +3,7 @@ package rocket
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import Chisel._
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import Node._;
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import Constants._;
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import collection.mutable._
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import collection.mutable.ArrayBuffer
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class Top extends Component
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{
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@ -4,17 +4,6 @@ import Chisel._
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import Node._
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import scala.math._
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object FillInterleaved
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{
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def apply(n: Int, in: Bits) =
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{
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var out = Fill(n, in(0))
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for (i <- 1 until in.getWidth)
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out = Cat(Fill(n, in(i)), out)
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out
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}
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}
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class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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{
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val io = new Bundle {
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@ -25,84 +14,3 @@ class Mux1H [T <: Data](n: Int)(gen: => T) extends Component
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io.out := Mux1H(io.sel, io.in)
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}
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class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new FIFOIO()) { data } }.flip
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val lock = Vec(n) { Bool() }.asInput
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val out = (new FIFOIO()) { data }
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}
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class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioLockingArbiter(n)(data)
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val locked = Vec(n) { Reg(resetVal = Bool(false)) }
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val any_lock_held = (locked.toBits & io.lock.toBits).orR
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val valid_arr = Vec(n) { Bool() }
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val bits_arr = Vec(n) { data }
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for(i <- 0 until n) {
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valid_arr(i) := io.in(i).valid
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bits_arr(i) := io.in(i).bits
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}
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io.in(0).ready := Mux(any_lock_held, io.out.ready && locked(0), io.out.ready)
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locked(0) := Mux(any_lock_held, locked(0), io.in(0).ready && io.lock(0))
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for (i <- 1 until n) {
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io.in(i).ready := Mux(any_lock_held, io.out.ready && locked(i),
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!io.in(i-1).valid && io.in(i-1).ready)
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locked(i) := Mux(any_lock_held, locked(i), io.in(i).ready && io.lock(i))
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}
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var dout = io.in(n-1).bits
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for (i <- 1 until n)
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dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
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var vout = io.in(0).valid
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for (i <- 1 until n)
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vout = vout || io.in(i).valid
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val lock_idx = PriorityEncoder(locked.toBits)
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io.out.valid := Mux(any_lock_held, valid_arr(lock_idx), vout)
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io.out.bits := Mux(any_lock_held, bits_arr(lock_idx), dout)
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}
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object PriorityMux
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{
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def apply[T <: Data](sel: Seq[Bits], in: Seq[T]): T = {
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if (in.size == 1)
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in.head
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else
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Mux(sel.head, in.head, apply(sel.tail, in.tail))
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}
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def apply[T <: Data](sel: Bits, in: Seq[T]): T = apply((0 until in.size).map(sel(_)), in)
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}
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object PriorityEncoder
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{
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def apply(in: Seq[Bits]): UFix = PriorityMux(in, (0 until in.size).map(UFix(_)))
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def apply(in: Bits): UFix = apply((0 until in.getWidth).map(in(_)))
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}
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object PriorityEncoderOH
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{
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def apply(in: Bits): Bits = Vec(apply((0 until in.getWidth).map(in(_)))){Bool()}.toBits
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def apply(in: Seq[Bits]): Seq[Bool] = {
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var none_hot = Bool(true)
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val out = collection.mutable.ArrayBuffer[Bool]()
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for (i <- 0 until in.size) {
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out += none_hot && in(i)
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none_hot = none_hot && !in(i)
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}
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out
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}
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}
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object Counter
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{
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def apply(cond: Bool, n: Int) = {
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val c = Reg(resetVal = UFix(0, log2Up(n)))
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val wrap = c === UFix(n-1)
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when (cond) {
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c := Mux(Bool(!isPow2(n)) && wrap, UFix(0), c + UFix(1))
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}
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(c, wrap && cond)
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}
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}
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