78 lines
2.7 KiB
Scala
78 lines
2.7 KiB
Scala
package rocket
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import Chisel._
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import Node._;
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import Constants._;
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new ioDebug();
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val host = new ioHost(htif_width);
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val host_clk = Bool(OUTPUT)
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val mem_backup = new ioMemSerialized
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val mem_backup_en = Bool(INPUT)
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val mem_backup_clk = Bool(OUTPUT)
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val mem = new ioMem
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}
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class Top extends Component
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{
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val clkdiv = 32
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val htif_width = 8
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val io = new ioTop(htif_width)
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val tile = new Tile
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val htif = new rocketHTIF(htif_width, 1)
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val hub = new CoherenceHubBroadcast(2)
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hub.io.tiles(0) <> tile.io.tilelink
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hub.io.tiles(1) <> htif.io.mem
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// mux between main and backup memory ports
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val mem_serdes = new MemSerdes
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val mem_cmdq = (new queue(1)) { new MemReqCmd }
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mem_cmdq.io.enq <> hub.io.mem.req_cmd
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mem_cmdq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_cmd.ready, io.mem.req_cmd.ready)
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io.mem.req_cmd.valid := mem_cmdq.io.deq.valid && !io.mem_backup_en
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io.mem.req_cmd.bits := mem_cmdq.io.deq.bits
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mem_serdes.io.wide.req_cmd.valid := mem_cmdq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_cmd.bits := mem_cmdq.io.deq.bits
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val mem_dataq = (new queue(2)) { new MemData }
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mem_dataq.io.enq <> hub.io.mem.req_data
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mem_dataq.io.deq.ready := Mux(io.mem_backup_en, mem_serdes.io.wide.req_data.ready, io.mem.req_data.ready)
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io.mem.req_data.valid := mem_dataq.io.deq.valid && !io.mem_backup_en
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io.mem.req_data.bits := mem_dataq.io.deq.bits
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mem_serdes.io.wide.req_data.valid := mem_dataq.io.deq.valid && io.mem_backup_en
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mem_serdes.io.wide.req_data.bits := mem_dataq.io.deq.bits
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hub.io.mem.resp.valid := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.valid, io.mem.resp.valid)
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hub.io.mem.resp.bits := Mux(io.mem_backup_en, mem_serdes.io.wide.resp.bits, io.mem.resp.bits)
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// pad out the HTIF using a divided clock
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val hio = (new slowIO(clkdiv, 4)) { Bits(width = htif_width) }
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htif.io.host.out <> hio.io.out_fast
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io.host.out <> hio.io.out_slow
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htif.io.host.in <> hio.io.in_fast
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io.host.in <> hio.io.in_slow
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io.host_clk := hio.io.clk_slow
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// pad out the backup memory link with the HTIF divided clk
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val mio = (new slowIO(clkdiv, 4)) { Bits(width = MEM_BACKUP_WIDTH) }
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mem_serdes.io.narrow.req <> mio.io.out_fast
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io.mem_backup.req <> mio.io.out_slow
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mem_serdes.io.narrow.resp.valid := mio.io.in_fast.valid
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mio.io.in_fast.ready := Bool(true)
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mem_serdes.io.narrow.resp.bits := mio.io.in_fast.bits
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io.mem_backup.resp <> mio.io.in_slow
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io.mem_backup_clk := mio.io.clk_slow
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tile.io.host <> htif.io.cpu(0)
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io.debug <> tile.io.host.debug
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}
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object top_main {
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def main(args: Array[String]) = {
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chiselMain(args.drop(1), () => Class.forName(args(0)).newInstance.asInstanceOf[Component])
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}
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}
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