Made xact_rep an ioValid, removed has_data member
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c7b01230f4
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@ -59,9 +59,7 @@ class rocketMemArbiter(n: Int) extends Component {
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io.requestor(i).xact_rep.valid := io.mem.xact_rep.valid && tag(log2up(n)-1,0) === UFix(i)
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io.requestor(i).xact_rep.bits.data := io.mem.xact_rep.bits.data
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io.requestor(i).xact_rep.bits.t_type := io.mem.xact_rep.bits.t_type
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io.requestor(i).xact_rep.bits.has_data := io.mem.xact_rep.bits.has_data
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io.requestor(i).xact_rep.bits.tile_xact_id := tag >> UFix(log2up(n))
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io.requestor(i).xact_rep.bits.global_xact_id := io.mem.xact_rep.bits.global_xact_id
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}
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io.mem.xact_rep.ready := Bool(true) // XXX we shouldn't have xact_rep.ready
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}
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@ -14,10 +14,9 @@ class MemReqCmd() extends Bundle
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val tag = Bits(width = MEM_TAG_BITS)
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}
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class MemResp () extends Bundle
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class MemResp () extends MemData
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{
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val tag = Bits(width = MEM_TAG_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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}
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class ioMem() extends Bundle
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@ -72,7 +71,6 @@ class ProbeReplyData extends MemData
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class TransactionReply extends MemData {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val global_xact_id = Bits(width = GLOBAL_XACT_ID_BITS)
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}
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@ -88,7 +86,7 @@ class ioTileLink extends Bundle {
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val probe_req = (new ioDecoupled) { new ProbeRequest() }
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val probe_rep = (new ioDecoupled) { new ProbeReply() }.flip
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val probe_rep_data = (new ioDecoupled) { new ProbeReplyData() }.flip
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val xact_rep = (new ioDecoupled) { new TransactionReply() }
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val xact_rep = (new ioValid) { new TransactionReply() }
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val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
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}
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@ -173,6 +171,10 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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state.toBits
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}
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def replyTypeHasData (reply: TransactionReply): Bool = {
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(reply.t_type != X_WRITE_UNCACHED)
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}
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}
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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@ -30,7 +30,7 @@ class Top() extends Component {
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// connect tile to hub
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hub.io.tiles(0).xact_init <> Queue(arbiter.io.mem.xact_init)
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hub.io.tiles(0).xact_init_data <> Queue(arbiter.io.mem.xact_init_data)
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arbiter.io.mem.xact_rep <> Queue(hub.io.tiles(0).xact_rep, 1, pipe = true)
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arbiter.io.mem.xact_rep <> PipeReg(hub.io.tiles(0).xact_rep)
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// connect hub to memory
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io.mem.req_cmd <> Queue(hub.io.mem.req_cmd)
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io.mem.req_data <> Queue(hub.io.mem.req_data)
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