Abstract base nbcache class
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@ -684,7 +684,18 @@ class ioDCache(view: List[String] = null) extends Bundle(view) {
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val resp_val = Bool(OUTPUT);
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}
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class HellaCache extends Component with ThreeStateIncoherence {
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abstract class HellaCache extends Component {
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def isHit ( cmd: Bits, state: UFix): Bool
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def isValid (state: UFix): Bool
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def needsWriteback (state: UFix): Bool
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def newStateOnWriteback(): UFix
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def newStateOnFlush(): UFix
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def newStateOnHit(cmd: Bits, state: UFix): UFix
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def newStateOnPrimaryMiss(cmd: Bits): UFix
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def newStateOnSecondaryMiss(cmd: Bits, state: UFix): UFix
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}
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class HellaCacheUniproc extends HellaCache with ThreeStateIncoherence {
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val io = new Bundle {
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val cpu = new ioDmem()
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val mem = new ioDCache().flip
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@ -18,7 +18,7 @@ class Top() extends Component {
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val icache = new rocketICache(128, 2); // 128 sets x 2 ways
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val icache_pf = new rocketIPrefetcher();
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val vicache = new rocketICache(128, 2); // 128 sets x 2 ways
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val dcache = new HellaCache();
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val dcache = new HellaCacheUniproc();
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val arbiter = new rocketMemArbiter();
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arbiter.io.mem <> io.mem;
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