riscv/rocket-chip
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  • 1be9d15944 Fixed bug regarding case sensitivity regarding ioICache,ioDCache Christopher Celio 2012-02-07 14:07:42 -0800
  • fde8e3b696 clean up bypassing/hazard checking a bit Andrew Waterman 2012-02-06 17:26:45 -0800
  • 41c4e10c37 Workaround for another frakking extraction error in the C backend. C and VLSI backends now both boot kernel with associativity on Henry Cook 2012-02-02 21:53:39 -0800
  • 99a959e6b1 remove pc+4 piperegs and add new ex pc+4 adder Andrew Waterman 2012-02-02 13:33:27 -0800
  • 01a156eb98 make # of dcache lines configurable Andrew Waterman 2012-02-01 21:11:45 -0800
  • b1bbf56b74 clean up wb->id bypass Andrew Waterman 2012-02-01 15:36:01 -0800
  • c5a4eaa0a1 Associative cache, boots kernel Henry Cook 2012-02-01 13:26:04 -0800
  • 281abfbccb New Mux1H constructor Henry Cook 2012-02-01 13:24:28 -0800
  • 38c9105ea1 fix mul/div deadlock bug Andrew Waterman 2012-01-30 21:14:28 -0800
  • bd241ea237 fix when badvaddr is set Andrew Waterman 2012-01-30 17:15:42 -0800
  • a96c92f58d enable amomin[u]/amomax[u Andrew Waterman 2012-01-26 20:45:04 -0800
  • a7999d4525 don't flush I$ unless fence.i commits Andrew Waterman 2012-01-26 20:36:31 -0800
  • 32f5f420f3 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Andrew Waterman 2012-01-26 20:12:42 -0800
  • 41855a6d47 fix missing "otherwise" in PCR file Andrew Waterman 2012-01-26 19:33:55 -0800
  • 7172ddd050 don't flush pipeline after MFPCR Andrew Waterman 2012-01-24 18:40:08 -0800
  • 97c379f1d7 made I$ associative Andrew Waterman 2012-01-24 16:51:30 -0800
  • aa3465699b LFSR now a util Henry Cook 2012-01-24 14:39:52 -0800
  • 7f26fe2c44 make icache size parameterizable Andrew Waterman 2012-01-24 15:13:49 -0800
  • 8229d65adf Associative cache passes asm tests and bmarks with power of 2 associativities (including 1) Henry Cook 2012-01-24 11:41:44 -0800
  • 9e6b86fe85 Fix a nasty replay bug Andrew Waterman 2012-01-24 03:40:01 -0800
  • 06fdf79dab fix long-latency writeback arbitration bug Andrew Waterman 2012-01-24 00:56:47 -0800
  • f1c355e3cd check pc/effective address sign extension Andrew Waterman 2012-01-24 00:15:17 -0800
  • a5a020f97b update chisel and remove SRAM_READ_LATENCY Andrew Waterman 2012-01-23 20:59:38 -0800
  • 8766438bb9 Updated chisel removes ^^ from language. Removed from rocket source, updated jar. Henry Cook 2012-01-23 09:51:35 -0800
  • e7bf07d55e fix AMO replay bug Andrew Waterman 2012-01-23 15:35:53 -0800
  • d59bddfbf1 fix I$ miss replay bug Andrew Waterman 2012-01-21 20:42:13 -0800
  • 31c56228e2 add missing "otherwise" Andrew Waterman 2012-01-21 20:13:15 -0800
  • 97f0852b17 DM cache with assoc-aware subunits passes all asm and bmarks Henry Cook 2012-01-18 17:53:26 -0800
  • 8623d58724 split into two caches, compiles Henry Cook 2012-01-18 15:07:36 -0800
  • 29ed8eb31a More utils for nbdcache Henry Cook 2012-01-17 23:49:32 -0800
  • 7e25749581 Groundwork for assoc cache implementation Henry Cook 2012-01-13 15:55:56 -0800
  • 07f184df2f adhere to new chisel c naming convention Andrew Waterman 2012-01-18 15:23:21 -0800
  • 1d76255dc1 new chisel version jar and find and replace INPUT and OUTPUT Henry Cook 2012-01-18 10:28:48 -0800
  • e4cf6391d7 fix i$ miss pathology and badvaddr bug Andrew Waterman 2012-01-17 23:47:35 -0800
  • 0369b05deb move replays to writeback stage Andrew Waterman 2012-01-17 21:12:31 -0800
  • 1c8f496811 fix fpga build Andrew Waterman 2012-01-13 20:04:11 -0800
  • addfe55735 add FPGA memory generator script Andrew Waterman 2012-01-13 18:18:48 -0800
  • acf3134e80 minor control logic cleanup Andrew Waterman 2012-01-12 14:19:18 -0800
  • 4807d7222b use replay to handle I$ misses Andrew Waterman 2012-01-11 19:20:20 -0800
  • 1a7bfd4350 remove icache req_rdy signal Andrew Waterman 2012-01-11 18:27:11 -0800
  • bcb55e581a remove host.start signal, use reset instead Andrew Waterman 2012-01-11 17:49:32 -0800
  • 92dda102b6 slight control logic cleanup Andrew Waterman 2012-01-11 16:56:40 -0800
  • 938b142d64 require writes to memory to be uninterrupted Andrew Waterman 2012-01-03 18:41:53 -0800
  • 142dfc6e07 made tohost/fromhost 64 bits wide Andrew Waterman 2012-01-03 15:09:08 -0800
  • 20aee36c96 move PCR writes to WB stage Andrew Waterman 2012-01-02 15:42:39 -0800
  • 3045b33460 remove second RF write port Andrew Waterman 2012-01-02 02:51:30 -0800
  • ffe23a1ee8 fix WAW hazard handling Andrew Waterman 2012-01-02 00:25:11 -0800
  • eb657dd250 reduce superfluous replays Andrew Waterman 2012-01-01 21:28:38 -0800
  • efc623cc36 validate BTB address and use BTB for J/JAL/JR/JALR Andrew Waterman 2012-01-01 17:04:14 -0800
  • 2f8fcebea0 remove datapath register resets resets Andrew Waterman 2012-01-01 16:09:40 -0800
  • f9160c53cf fixes for correct verilog generation Andrew Waterman 2011-12-29 23:46:21 -0800
  • 1028ff7d9b fix multiplier bug Andrew Waterman 2011-12-29 23:45:09 -0800
  • d65e1a2eee vlsi verilog compiles now but doesn't simulate Andrew Waterman 2011-12-20 22:08:27 -0800
  • 38ea10a5f4 parameterized multiplier unrolling Andrew Waterman 2011-12-20 04:18:28 -0800
  • 733fc8e65e booth multiplier Andrew Waterman 2011-12-20 03:49:07 -0800
  • b5a8b6dc73 fix divider for RV32 Andrew Waterman 2011-12-19 16:57:53 -0800
  • bcceb08373 add dummy mul_rdy signal Andrew Waterman 2011-12-17 07:30:47 -0800
  • 96c78829b4 improve ALU and fix revealed emulator bug Andrew Waterman 2011-12-17 07:20:32 -0800
  • 82700cad72 fix multiplier for rv32 Andrew Waterman 2011-12-17 07:20:00 -0800
  • a8d0cd95e6 hellacache now works Andrew Waterman 2011-12-17 03:26:11 -0800
  • 56c4f44c2a hellacache returns! Andrew Waterman 2011-12-12 06:49:16 -0800
  • 0ea2704b80 new mftx instruction format Yunsup Lee 2011-12-12 03:23:12 -0800
  • 8308345364 work in progress on hellacache Andrew Waterman 2011-12-10 07:01:47 -0800
  • ce201559f3 Support cache->cpu nacks one cycle after request Andrew Waterman 2011-12-10 00:42:09 -0800
  • c01e1f1cef Don't replay from EX stage. Andrew Waterman 2011-12-09 19:42:58 -0800
  • 218f63e66e code cleanup/parameterization Andrew Waterman 2011-12-09 00:42:43 -0800
  • a87ad06780 Automatically infer rocketCAM address width Andrew Waterman 2011-12-05 15:45:44 -0800
  • fa784d1d7d made setReadLatency argument a parameter defined in consts.scala Rimas Avizienis 2011-12-05 00:33:17 -0800
  • ff95cacb55 icache/dcache tag+data arrays now implemented using Mem4() however there seems to be a bug - readLatency needs to be set to 0 for C model to work, and 1 for Verilog model. Rimas Avizienis 2011-12-04 01:18:38 -0800
  • e894b79870 caches now use Mem4() memories for tag+data arrays Rimas Avizienis 2011-12-03 19:41:15 -0800
  • c580180b66 tweaks to cache/SRAM interface for TSMC65 SRAMs Rimas Avizienis 2011-12-02 02:01:08 -0800
  • e70b41241c changed branch addr generation to get it off critical path Rimas Avizienis 2011-12-02 01:56:17 -0800
  • cf1965493b renamed SRAM modules to match TSMC65 MC generated SRAMs Rimas Avizienis 2011-12-01 13:14:33 -0800
  • da2fdf4f85 fixed console i/o Rimas Avizienis 2011-11-30 22:51:59 -0800
  • b2894671f6 Merge branch 'master' of github.com:ucb-bar/riscv-rocket Rimas Avizienis 2011-11-30 21:55:13 -0800
  • bc44572d99 bugfixes due to new hcl jar file Rimas Avizienis 2011-11-30 21:54:55 -0800
  • 8f3927fdfa queue data type is now templated Andrew Waterman 2011-11-30 18:07:57 -0800
  • 11f0e3daf4 more cleanup Rimas Avizienis 2011-11-18 00:17:30 -0800
  • c42d8149b7 moved PCR writeback to end of MEM stage, cleanup of dcache/dpath/ctrl Rimas Avizienis 2011-11-17 23:50:45 -0800
  • 5a322ff00c fixed dtlb bug (swapped r/w permissions), added fake mtfsr/mffsr/fld/fst instructions Rimas Avizienis 2011-11-17 11:17:37 -0800
  • 80b4253318 fixed dcache amo bug, cleaned up testharness, added RDTIME instruction Rimas Avizienis 2011-11-16 02:04:28 -0800
  • 886857fa47 writes of PC weren't being sign extended Rimas Avizienis 2011-11-15 18:07:36 -0800
  • fc0f20643a cleanup Rimas Avizienis 2011-11-15 18:06:41 -0800
  • ae98956e6b more amo fixes, added more options to testharness to control debug messages Rimas Avizienis 2011-11-15 02:43:51 -0800
  • 82a636ff55 AMOADD, AMOAND, AMOOR, AMOSWAP working Rimas Avizienis 2011-11-15 00:51:45 -0800
  • 48cec01710 updated riscv-bmarks and riscv-tests to build with new toolchain Rimas Avizienis 2011-11-15 00:11:22 -0800
  • db87924fbf made eret instruction take an illegal inst exception when ET is set Rimas Avizienis 2011-11-14 14:35:10 -0800
  • cd6e463320 added ei and di instructions Rimas Avizienis 2011-11-14 13:48:49 -0800
  • b791010bb1 flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs Rimas Avizienis 2011-11-14 04:13:13 -0800
  • 890bfa7c48 added IPIs and timer interrupts Rimas Avizienis 2011-11-14 03:24:02 -0800
  • 5b29765917 synced up with supervisor mode state in latest ISA simulator Rimas Avizienis 2011-11-14 01:37:20 -0800
  • 9d3471a569 more cache fixes, more test harness debug output Rimas Avizienis 2011-11-13 23:32:18 -0800
  • 67c7e7e28f cache/tlb bugfixes, increased memory size to 256meg Rimas Avizienis 2011-11-13 13:06:35 -0800
  • 29d44b8bc5 fixed typo that broke illegal instruction exception Rimas Avizienis 2011-11-13 01:17:33 -0800
  • 7b3c34a341 regenerated instruction encodings using parse-opcodes Rimas Avizienis 2011-11-13 00:59:02 -0800
  • 44419511b7 timer interrupt fixes Rimas Avizienis 2011-11-13 00:32:08 -0800
  • 345f950eff added timer interrupt support Rimas Avizienis 2011-11-13 00:27:57 -0800
  • 5f4b15b809 added ld/st misaligned exceptions Rimas Avizienis 2011-11-13 00:03:17 -0800
  • fbd44ea936 added checks for addresses > physical memory size, increased memsize to 64M Rimas Avizienis 2011-11-12 23:39:43 -0800
  • 35af912bd2 cache optimizations, cleanup, and testharness improvement Rimas Avizienis 2011-11-12 22:13:29 -0800