fix I$ miss replay bug
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@ -592,7 +592,7 @@ class rocketCtrl extends Component
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io.dpath.wen_btb := !ex_btb_match && br_jr_taken;
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io.dpath.clr_btb := ex_reg_btb_hit && !br_jr_taken || id_reg_icmiss;
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io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_icmiss)
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io.imem.req_val := take_pc_wb || !mem_reg_replay && !ex_reg_replay && (take_pc_ex || !id_reg_replay)
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// stall for RAW/WAW hazards on loads, AMOs, and mul/div in execute stage.
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val ex_mem_cmd_load =
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