riscv/rocket-chip
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added timer interrupt support

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This commit is contained in:
Rimas Avizienis 2011-11-13 00:27:57 -08:00
parent 5f4b15b809
commit 345f950eff
2 changed files with 21 additions and 15 deletions
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10
rocket/src/main/scala/ctrl.scala
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@ -75,6 +75,7 @@ class ioCtrlAll extends Bundle()
val xcpt_itlb = Bool('input);
val xcpt_ma_ld = Bool('input);
val xcpt_ma_st = Bool('input);
val timer_int = Bool('input);
}
class rocketCtrl extends Component
@ -382,7 +383,12 @@ class rocketCtrl extends Component
}
// exception handling
// FIXME: verify PC in MEM stage points to valid, restartable instruction
val interrupt = io.dpath.status(SR_ET).toBool && io.dpath.status(15).toBool && io.timer_int;
val interrupt_cause = UFix(0x17, 5);
val mem_exception =
interrupt ||
io.xcpt_ma_ld ||
io.xcpt_ma_st ||
io.xcpt_dtlb_ld ||
@ -395,18 +401,18 @@ class rocketCtrl extends Component
mem_reg_xcpt_ma_inst;
val mem_cause =
Mux(interrupt, interrupt_cause, // asynchronous interrupt
Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
// interrupt
Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
// breakpoint
Mux(io.xcpt_ma_ld, UFix(8,5), // misaligned load
Mux(io.xcpt_ma_st, UFix(9,5), // misaligned store
Mux(io.xcpt_dtlb_ld, UFix(10,5), // load fault
Mux(io.xcpt_dtlb_st, UFix(11,5), // store fault
UFix(0,5)))))))))); // instruction address misaligned
UFix(0,5))))))))))); // instruction address misaligned
// write cause to PCR on an exception
io.dpath.exception := mem_exception;

26
rocket/src/main/scala/dpath_util.scala
View File

@ -35,15 +35,6 @@ class rocketDpathBTB(entries: Int) extends Component
io.hit := (is_val & (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1))).toBool;
io.target := Cat(tag_target(taglsb-1, 0), Bits(0,idxlsb)).toUFix;
// val rst_lwlr_pf = Mem(entries, io.wen, io.correct_pc4(3, 2), UFix(1, 1), resetVal = UFix(0, 1));
// val lwlr_pf = Mem(entries, io.wen, io.correct_pc4(3, 2),
// Cat(io.correct_pc4(VADDR_BITS-1,4), io.correct_target(VADDR_BITS-1,2)), resetVal = UFix(0, 1));
// val is_val = rst_lwlr_pf(io.current_pc4(3, 2));
// val tag_target = lwlr_pf(io.current_pc4(3, 2));
//
// io.hit := (is_val & (tag_target(2*VADDR_BITS-7,VADDR_BITS-2) === io.current_pc4(VADDR_BITS-1, 4))).toBool;
// io.target := Cat(tag_target(VADDR_BITS-3, 0), Bits(0,2)).toUFix;
}
class ioDpathPCR extends Bundle()
@ -62,6 +53,7 @@ class ioDpathPCR extends Bundle()
val pc = UFix(VADDR_BITS, 'input);
val badvaddr = UFix(VADDR_BITS, 'input);
val eret = Bool('input);
val timer_int = Bool('output);
}
class rocketDpathPCR extends Component
@ -71,8 +63,8 @@ class rocketDpathPCR extends Component
val reg_epc = Reg(resetVal = UFix(0, VADDR_BITS));
val reg_badvaddr = Reg(resetVal = UFix(0, VADDR_BITS));
val reg_ebase = Reg(resetVal = UFix(0, VADDR_BITS));
val reg_count = Reg(resetVal = Bits(0, 32));
val reg_compare = Reg(resetVal = Bits(0, 32));
val reg_count = Reg(resetVal = UFix(0, 32));
val reg_compare = Reg(resetVal = UFix(0, 32));
val reg_cause = Reg(resetVal = Bits(0, 5));
val reg_tohost = Reg(resetVal = Bits(0, 32));
val reg_fromhost = Reg(resetVal = Bits(0, 32));
@ -91,6 +83,8 @@ class rocketDpathPCR extends Component
val reg_status_ps = Reg(resetVal = Bool(false));
val reg_status_et = Reg(resetVal = Bool(false));
val timer_interrupt = Reg(resetVal = Bool(false));
val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, Bits(0,1), reg_status_ev, reg_status_ef, reg_status_et);
val rdata = Wire() { Bits() };
@ -148,8 +142,8 @@ class rocketDpathPCR extends Component
when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_EVEC) { reg_ebase <== io.w.data(VADDR_BITS-1,0).toUFix; }
when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(31,0); }
when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0); }
when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(31,0).toUFix; }
when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0).toUFix; timer_interrupt <== Bool(false); }
when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); }
when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data(31,0); }
when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
@ -157,6 +151,12 @@ class rocketDpathPCR extends Component
when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
}
reg_count <== reg_count + UFix(1);
when (reg_count === reg_compare) {
timer_interrupt <== Bool(true);
}
io.timer_int := timer_interrupt;
when (!io.r.en) { rdata <== Bits(0,64); }
switch (io.r.addr) {
is (PCR_STATUS) { rdata <== Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); }