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cache/tlb bugfixes, increased memory size to 256meg

This commit is contained in:
Rimas Avizienis 2011-11-13 13:06:35 -08:00
parent 29d44b8bc5
commit 67c7e7e28f
4 changed files with 5 additions and 5 deletions
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2
rocket/src/main/scala/consts.scala
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@ -182,7 +182,7 @@ object Constants
// physical memory size (# 8K pages)
// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
val MEMSIZE_PAGES = 8192; // 64 megs
val MEMSIZE_PAGES = 0x8000; // 256 megs
val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
val HAVE_FPU = Bool(false);

2
rocket/src/main/scala/ctrl.scala
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@ -422,8 +422,8 @@ class rocketCtrl extends Component
// replay mem stage PC on a DTLB miss
val replay_mem = io.dtlb_miss;
val kill_ex = replay_ex || replay_mem;
val kill_mem = mem_exception || replay_mem;
val kill_ex = replay_ex || kill_mem;
io.dpath.sel_pc :=
Mux(replay_mem, PC_MEM, // dtlb miss

4
rocket/src/main/scala/dcache.scala
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@ -352,8 +352,8 @@ class rocketDCacheDM(lines: Int) extends Component {
r_cpu_resp_val;
val misaligned =
((r_cpu_req_type === MT_H) && r_cpu_req_idx(0).toBool) ||
((r_cpu_req_type === MT_W) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && r_cpu_req_idx(0).toBool) ||
(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0,2))) ||
((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0,3)));
io.cpu.xcpt_ma_ld := r_cpu_req_val && r_req_load && misaligned;

2
rocket/src/main/scala/itlb.scala
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@ -177,7 +177,7 @@ class rocketITLB(entries: Int) extends Component
((status_s && !sx_array(tag_hit_addr).toBool) ||
(status_u && !ux_array(tag_hit_addr).toBool));
io.cpu.exception := access_fault || outofrange;
io.cpu.exception := access_fault; //|| outofrange;
io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
io.cpu.resp_miss := tlb_miss || (state != s_ready);
io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;