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@ -541,7 +541,7 @@ class AMOALU extends Component {
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}
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class HellaCache(lines: Int) extends Component {
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val io = new ioDCacheDM();
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val io = new ioDCacheHella();
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val addrbits = PADDR_BITS;
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val indexbits = log2up(lines);
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@ -602,6 +602,22 @@ class HellaCache(lines: Int) extends Component {
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}
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}
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// refill counter
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val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val rr_count_next = rr_count + UFix(1)
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when (io.mem.resp_val) { rr_count <== rr_count_next }
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val misaligned =
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(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
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(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
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io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
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}
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class HellaCacheDM(lines: Int) extends HellaCache(lines) {
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// tags
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val meta = new MetaDataArray(lines)
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val meta_arb = (new Arbiter(3)) { new MetaArrayReq() }
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@ -632,11 +648,6 @@ class HellaCache(lines: Int) extends Component {
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val tag_miss = r_cpu_req_val && !tag_match
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val dirty = meta.io.resp.valid && meta.io.resp.dirty
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// refill counter
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val rr_count = Reg(resetVal = UFix(0, log2up(REFILL_CYCLES)))
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val rr_count_next = rr_count + UFix(1)
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when (io.mem.resp_val) { rr_count <== rr_count_next }
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// refill response
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val block_during_refill = !io.mem.resp_val && (rr_count != UFix(0))
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data_arb.io.in(0).valid := io.mem.resp_val || block_during_refill
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@ -791,14 +802,6 @@ class HellaCache(lines: Int) extends Component {
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io.cpu.resp_data := loadgen.io.dout
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io.cpu.resp_data_subword := loadgen.io.r_dout_subword
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val misaligned =
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(((r_cpu_req_type === MT_H) || (r_cpu_req_type === MT_HU)) && (r_cpu_req_idx(0) != Bits(0))) ||
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(((r_cpu_req_type === MT_W) || (r_cpu_req_type === MT_WU)) && (r_cpu_req_idx(1,0) != Bits(0))) ||
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((r_cpu_req_type === MT_D) && (r_cpu_req_idx(2,0) != Bits(0)));
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io.cpu.xcpt_ma_ld := r_cpu_req_val_ && r_req_read && misaligned
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io.cpu.xcpt_ma_st := r_cpu_req_val_ && r_req_write && misaligned
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wb.io.mem_req.ready := io.mem.req_rdy
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io.mem.req_val := wb.io.mem_req.valid
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io.mem.req_rw := wb.io.mem_req.bits.rw
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