riscv/rocket-chip
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adhere to new chisel c naming convention

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This commit is contained in:
Andrew Waterman 2012-01-18 15:23:21 -08:00
parent 1d76255dc1
commit 07f184df2f
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/top.scala
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@ -37,9 +37,9 @@ class Top() extends Component {
object top_main {
def main(args: Array[String]) = {
// Can turn off --debug and --vcd when done with debugging to improve emulator performance
val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
// val cpu_args = args ++ Array("--target-dir", "generated-src","--debug","--vcd");
// val cpu_args = args ++ Array("--target-dir", "generated-src", "--debug");
// val cpu_args = args ++ Array("--target-dir", "generated-src");
val cpu_args = args ++ Array("--target-dir", "generated-src");
// Set variables based off of command flags
// for(a <- args) {
// a match {