added checks for addresses > physical memory size, increased memsize to 64M
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35af912bd2
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@ -180,10 +180,10 @@ object Constants
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val DTLB_ENTRIES = 8;
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val ITLB_ENTRIES = 8;
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// physical memory size (# 4K pages - for proxy kernel at least)
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// physical memory size (# 8K pages)
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// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
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val MEMSIZE_PAGES = 8192; // 32 megs
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val MEMSIZE = MEMSIZE_PAGES*4096;
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val MEMSIZE_PAGES = 8192; // 64 megs
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val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
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val HAVE_FPU = Bool(false);
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val HAVE_VEC = Bool(false);
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@ -119,8 +119,9 @@ class rocketDTLB(entries: Int) extends Component
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val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
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val lookup_hit = (state === s_ready) && r_cpu_req_val && !req_flush && tag_hit;
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val lookup_miss = (state === s_ready) && r_cpu_req_val && !req_flush && !tag_hit;
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val lookup = (state === s_ready) && r_cpu_req_val && !req_flush;
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val lookup_hit = lookup && tag_hit;
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val lookup_miss = lookup && !tag_hit;
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val tlb_hit = status_vm && lookup_hit;
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val tlb_miss = status_vm && lookup_miss;
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@ -134,17 +135,25 @@ class rocketDTLB(entries: Int) extends Component
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}
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}
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// FIXME: add check for out of range physical addresses (>MEMSIZE)
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io.cpu.xcpt_ld :=
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// exception check
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val outofrange = (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
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val access_fault_ld =
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tlb_hit && req_load &&
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((status_s && !sr_array(tag_hit_addr).toBool) ||
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(status_u && !ur_array(tag_hit_addr).toBool));
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io.cpu.xcpt_st :=
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io.cpu.xcpt_ld :=
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(lookup && req_load && outofrange) || access_fault_ld;
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val access_fault_st =
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tlb_hit && req_store &&
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((status_s && !sw_array(tag_hit_addr).toBool) ||
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(status_u && !uw_array(tag_hit_addr).toBool));
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io.cpu.xcpt_st :=
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(lookup && req_store && outofrange) || access_fault_st;
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
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io.cpu.resp_busy := tlb_miss || (state != s_ready);
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io.cpu.resp_miss := tlb_miss;
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@ -155,8 +155,9 @@ class rocketITLB(entries: Int) extends Component
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val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
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val lookup_hit = (state === s_ready) && r_cpu_req_val && tag_hit;
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val lookup_miss = (state === s_ready) && r_cpu_req_val && !tag_hit;
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val lookup = (state === s_ready) && r_cpu_req_val;
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val lookup_hit = lookup && tag_hit;
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val lookup_miss = lookup && !tag_hit;
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val tlb_hit = status_vm && lookup_hit;
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val tlb_miss = status_vm && lookup_miss;
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@ -168,12 +169,15 @@ class rocketITLB(entries: Int) extends Component
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}
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}
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// FIXME: add test for out of range physical addresses (> MEMSIZE)
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io.cpu.exception :=
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// exception check
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val outofrange = (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
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val access_fault =
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tlb_hit &&
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((status_s && !sx_array(tag_hit_addr).toBool) ||
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(status_u && !ux_array(tag_hit_addr).toBool));
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io.cpu.exception := access_fault || outofrange;
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io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
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io.cpu.resp_miss := tlb_miss || (state != s_ready);
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io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;
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