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added checks for addresses > physical memory size, increased memsize to 64M

This commit is contained in:
Rimas Avizienis 2011-11-12 23:39:43 -08:00
parent 35af912bd2
commit fbd44ea936
3 changed files with 26 additions and 13 deletions
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6
rocket/src/main/scala/consts.scala
View File

@ -180,10 +180,10 @@ object Constants
val DTLB_ENTRIES = 8;
val ITLB_ENTRIES = 8;
// physical memory size (# 4K pages - for proxy kernel at least)
// physical memory size (# 8K pages)
// if you change this value, make sure to also change MEMORY_SIZE variable in memif.h
val MEMSIZE_PAGES = 8192; // 32 megs
val MEMSIZE = MEMSIZE_PAGES*4096;
val MEMSIZE_PAGES = 8192; // 64 megs
val MEMSIZE_BYTES = MEMSIZE_PAGES*8192;
val HAVE_FPU = Bool(false);
val HAVE_VEC = Bool(false);

19
rocket/src/main/scala/dtlb.scala
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@ -119,8 +119,9 @@ class rocketDTLB(entries: Int) extends Component
val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
val lookup_hit = (state === s_ready) && r_cpu_req_val && !req_flush && tag_hit;
val lookup_miss = (state === s_ready) && r_cpu_req_val && !req_flush && !tag_hit;
val lookup = (state === s_ready) && r_cpu_req_val && !req_flush;
val lookup_hit = lookup && tag_hit;
val lookup_miss = lookup && !tag_hit;
val tlb_hit = status_vm && lookup_hit;
val tlb_miss = status_vm && lookup_miss;
@ -134,17 +135,25 @@ class rocketDTLB(entries: Int) extends Component
}
}
// FIXME: add check for out of range physical addresses (>MEMSIZE)
io.cpu.xcpt_ld :=
// exception check
val outofrange = (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
val access_fault_ld =
tlb_hit && req_load &&
((status_s && !sr_array(tag_hit_addr).toBool) ||
(status_u && !ur_array(tag_hit_addr).toBool));
io.cpu.xcpt_st :=
io.cpu.xcpt_ld :=
(lookup && req_load && outofrange) || access_fault_ld;
val access_fault_st =
tlb_hit && req_store &&
((status_s && !sw_array(tag_hit_addr).toBool) ||
(status_u && !uw_array(tag_hit_addr).toBool));
io.cpu.xcpt_st :=
(lookup && req_store && outofrange) || access_fault_st;
io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && !tlb_miss, Bool(true));
io.cpu.resp_busy := tlb_miss || (state != s_ready);
io.cpu.resp_miss := tlb_miss;

14
rocket/src/main/scala/itlb.scala
View File

@ -155,8 +155,9 @@ class rocketITLB(entries: Int) extends Component
val repl_waddr = Mux(invalid_entry, ie_addr, repl_count).toUFix;
val lookup_hit = (state === s_ready) && r_cpu_req_val && tag_hit;
val lookup_miss = (state === s_ready) && r_cpu_req_val && !tag_hit;
val lookup = (state === s_ready) && r_cpu_req_val;
val lookup_hit = lookup && tag_hit;
val lookup_miss = lookup && !tag_hit;
val tlb_hit = status_vm && lookup_hit;
val tlb_miss = status_vm && lookup_miss;
@ -168,12 +169,15 @@ class rocketITLB(entries: Int) extends Component
}
}
// FIXME: add test for out of range physical addresses (> MEMSIZE)
io.cpu.exception :=
// exception check
val outofrange = (io.cpu.resp_ppn > UFix(MEMSIZE_PAGES, PPN_BITS));
val access_fault =
tlb_hit &&
((status_s && !sx_array(tag_hit_addr).toBool) ||
(status_u && !ux_array(tag_hit_addr).toBool));
io.cpu.exception := access_fault || outofrange;
io.cpu.req_rdy := Mux(status_vm, (state === s_ready) && (!r_cpu_req_val || tag_hit), Bool(true));
io.cpu.resp_miss := tlb_miss || (state != s_ready);
io.cpu.resp_ppn := Mux(status_vm, tag_ram(tag_hit_addr), r_cpu_req_vpn(PPN_BITS-1,0)).toUFix;