riscv/rocket-chip
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  • c55eee7244 Pass target machine exit code back to host OS Andrew Waterman 2013-10-29 13:24:09 -0700
  • 12f0369e6e Simplify divide early out circuitry Andrew Waterman 2013-10-29 04:14:35 -0700
  • b44dafbdca Simplify branch offset mux Andrew Waterman 2013-10-29 04:13:50 -0700
  • 23f7bab4f3 Reduce FMA pipeline depths Andrew Waterman 2013-10-25 15:27:24 -0700
  • f440df5338 rename M_FENCE to M_NOP Yunsup Lee 2013-10-28 22:37:41 -0700
  • 1583560757 fix replay bug, don't respond when cmd is a NOP Yunsup Lee 2013-10-28 22:35:18 -0700
  • 437f7ed4af Push hardfloat (ignore target files) Stephen Twigg 2013-09-26 20:51:19 -0700
  • fc9c676fc1 add chisel and hardfloat back as sub-projects, bump other sub-projects Henry Cook 2013-09-26 12:01:46 -0700
  • 42693d43ad simplify build.sbt Henry Cook 2013-09-26 09:51:14 -0700
  • f6d7e22c46 Push rocket (fix issue with uppermost bit of D$ req tag getting lost) Stephen Twigg 2013-09-25 11:52:01 -0700
  • 36b85b8ee2 Fix issue where the MSB of D$ req tag was getting lost for all agents when an accelerator was attached. Stephen Twigg 2013-09-25 11:51:10 -0700
  • 36dfff5ee8 Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy. Stephen Twigg 2013-09-25 01:21:41 -0700
  • 891e459625 Export stats pcr register (#28 currently) to the top-level Stephen Twigg 2013-09-25 01:16:32 -0700
  • eb7e6f03b3 push rocket (AccumulatorExample fixes and documentation) Stephen Twigg 2013-09-24 16:33:32 -0700
  • 730a6ec76b AccumulatorExample now properly sets its busy bit. Also, pepper some helpful comments into AccumulatorExample Stephen Twigg 2013-09-24 16:32:49 -0700
  • 472b947fbe push rocket (add option to RocketConfiguration, vm, to turn off virtualk memory) Stephen Twigg 2013-09-24 16:16:12 -0700
  • eb03f61058 Properly ignore target files. Push uncore (properly ignore target files) Stephen Twigg 2013-09-24 16:03:28 -0700
  • 20246b373e Properly ignore target files Stephen Twigg 2013-09-24 16:02:00 -0700
  • 81c752de84 Support disabling virtual memory Andrew Waterman 2013-09-24 13:58:23 -0700
  • adc386f889 Turn off virtual memory inside RoCC base class Andrew Waterman 2013-09-24 13:53:49 -0700
  • 081fcc4e63 push rocket (accelerator interface fixes) Stephen Twigg 2013-09-24 10:55:22 -0700
  • 3532ae0b79 From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator). Stephen Twigg 2013-09-24 10:54:09 -0700
  • fba0ae0fec Push rocket Stephen Twigg 2013-09-23 00:26:27 -0700
  • db1e09f0d0 Fix issues with RoCC AccumulatorExample stalls on memory interface Stephen Twigg 2013-09-23 00:21:43 -0700
  • 324a6321bd Push tools (improve consistency: these tools will compile/test the new ISA encoding) Stephen Twigg 2013-09-22 03:24:11 -0700
  • 2676ea8279 Push rocket (fix some issues with RoCC although some remain) Stephen Twigg 2013-09-22 03:19:43 -0700
  • 158cee08af Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads) Stephen Twigg 2013-09-22 03:18:06 -0700
  • b7d7ced41b Update to new ISA Andrew Waterman 2013-09-21 06:40:23 -0700
  • 1d2f4f8437 New ISA encoding, AUIPC semantics Andrew Waterman 2013-09-21 06:32:40 -0700
  • 09247c0e0b fix to sram init pins Huy Vo 2013-09-19 20:12:10 -0700
  • c9813603ee Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 Huy Vo 2013-09-19 20:11:11 -0700
  • cc3dc1bd0f bug fix Huy Vo 2013-09-19 20:10:56 -0700
  • 9bf10ae5d2 remove extraneous toBits (need new Chisel) Andrew Waterman 2013-09-19 15:26:36 -0700
  • 42970c9a99 Update Rocket Andrew Waterman 2013-09-15 04:39:52 -0700
  • 25ab402932 swap JAL, JALR encodings Andrew Waterman 2013-09-15 04:29:06 -0700
  • 628745226c Use spike disassembler riscv-dis if it exists Andrew Waterman 2013-09-15 04:25:53 -0700
  • 80003b3019 Support RoCC Andrew Waterman 2013-09-15 04:25:26 -0700
  • 110e53cb48 Revert "Add early out to multiplier" Andrew Waterman 2013-09-15 04:15:32 -0700
  • 88d1c47665 don't disassemble within chisel Andrew Waterman 2013-09-15 04:14:45 -0700
  • f12bbc1e43 working RoCC AccumulatorExample Andrew Waterman 2013-09-14 22:34:53 -0700
  • 18968dfbc7 Move store data generation into cache Andrew Waterman 2013-09-14 16:15:07 -0700
  • a0cb711451 Start adding RoCC Andrew Waterman 2013-09-14 15:31:50 -0700
  • d053bdc89f Remove Hwacha from Rocket Andrew Waterman 2013-09-12 22:34:38 -0700
  • 1edb1e2a0a Ignore LSB of PC Andrew Waterman 2013-09-12 17:55:58 -0700
  • fbdbb01232 update to new isa; disable vector tests Andrew Waterman 2013-09-12 17:03:38 -0700
  • cc7783404d Add memory command M_XA_XOR Andrew Waterman 2013-09-12 16:09:53 -0700
  • 59f5358435 Implement AQ/RL; move fence logic out of cache Andrew Waterman 2013-09-12 16:07:30 -0700
  • 243c4ae342 sync up rocket with new isa Andrew Waterman 2013-09-12 03:44:38 -0700
  • 95dd0d8be1 Remove DebugIO/error mode Andrew Waterman 2013-09-11 20:15:21 -0700
  • b42e140e05 NetworkIOs no longer use thunks Henry Cook 2013-09-10 16:23:52 -0700
  • 1cac26fd76 NetworkIOs no longer use thunks Henry Cook 2013-09-10 16:15:41 -0700
  • f9b85d8158 NetworkIOs no longer use thunks Henry Cook 2013-09-10 16:15:19 -0700
  • ee98cd8378 new enum syntax Henry Cook 2013-09-10 10:54:51 -0700
  • d06e24ac24 new enum syntax Henry Cook 2013-09-10 10:51:35 -0700
  • 6cde69e95d Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc. Stephen Twigg 2013-09-09 14:31:18 -0700
  • cfbfa6b895 Add errors due to merge issues. Note, DebugIO re-introduced here but slated for possible removal in later commits. Stephen Twigg 2013-09-05 19:22:34 -0700
  • e23e8e3850 Merge branch 'master' into chisel-v2 Stephen Twigg 2013-09-05 16:17:34 -0700
  • d896ccbd43 Merge branch 'master' into chisel-v2 Stephen Twigg 2013-09-05 16:11:53 -0700
  • f27c0fb010 Merge commit '2bd4a66eee572252ba6250f9bddada51657fc379' into chisel-v2 Stephen Twigg 2013-09-05 15:01:56 -0700
  • 69daae0dae Add dependency resolvers to build.scala to fix build script Stephen Twigg 2013-09-05 14:56:41 -0700
  • 2c47b4388a push rocket Yunsup Lee 2013-08-26 14:54:49 -0700
  • b9f6e1a7ec Don't update BTB when garbage was fetched Andrew Waterman 2013-08-24 14:40:13 -0700
  • 9003bc2614 push rocket Yunsup Lee 2013-08-24 22:42:57 -0700
  • 44e92edf92 fix scr parameterization bug Yunsup Lee 2013-08-24 22:42:51 -0700
  • d0674af13f forgot to push riscv-rocket Yunsup Lee 2013-08-24 22:15:38 -0700
  • 3895b75a56 Support non-power-of-2 BTBs; prefer invalid entries Andrew Waterman 2013-08-24 17:33:11 -0700
  • ba9bbc27df apply same change to fpga top-level Yunsup Lee 2013-08-24 15:50:03 -0700
  • 76cd90fc01 parameterize number of SCRs Yunsup Lee 2013-08-24 15:47:42 -0700
  • 2ca5127785 parameterize number of SCRs Yunsup Lee 2013-08-24 15:47:14 -0700
  • 694ebd65cf push uncore Yunsup Lee 2013-08-24 15:24:25 -0700
  • b01fe4f6aa fix memserdes bit ordering Yunsup Lee 2013-08-24 15:24:17 -0700
  • daf23b8f79 Add early out to multiplier Andrew Waterman 2013-08-24 14:42:50 -0700
  • 67f80ba4b2 Stall div/mul writeback until WB slot is free Andrew Waterman 2013-08-24 14:40:57 -0700
  • d1b5076fee Don't update BTB when garbage was fetched Andrew Waterman 2013-08-24 14:40:13 -0700
  • 52e31f3298 Bypass scoreboard updates Andrew Waterman 2013-08-24 14:39:23 -0700
  • d4a0db4575 Reflect ISA changes Andrew Waterman 2013-08-23 21:16:28 -0700
  • 0884bc9789 fix DRAMSideLLCNull entries Yunsup Lee 2013-08-24 13:20:38 -0700
  • 1e3ac0afa9 back to NTILES=1 Yunsup Lee 2013-08-24 13:10:30 -0700
  • 9aff60f340 whitespace error in build.sbt Henry Cook 2013-08-21 16:16:42 -0700
  • dc53529156 added resolver, bumped chisel dependency Henry Cook 2013-08-21 16:00:51 -0700
  • 6aa500fc16 dont make assumptions about default project name when invoking sbt Henry Cook 2013-08-20 12:56:01 -0700
  • b06d33da2f Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes Henry Cook 2013-08-19 19:54:41 -0700
  • ff7b486006 standardized sbt build Henry Cook 2013-08-15 18:13:19 -0700
  • 85e5ce046f pulled submodule commits, uncore sbt standardized Henry Cook 2013-08-15 17:07:13 -0700
  • 6b20556661 Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2 Henry Cook 2013-08-15 16:39:30 -0700
  • 784e017bae Final Reg standardization Henry Cook 2013-08-15 16:37:58 -0700
  • ae02ebd153 Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2 Henry Cook 2013-08-15 16:35:27 -0700
  • b80f45f8f2 Merge branch 'chisel-v2' of github.com:ucb-bar/uncore into chisel-v2 Henry Cook 2013-08-15 16:22:12 -0700
  • 3763cd0004 standardizing sbt build conventions Henry Cook 2013-08-15 15:57:16 -0700
  • 3a266cbbfa final Reg changes Henry Cook 2013-08-15 15:28:15 -0700
  • 17d404b325 final Reg changes Henry Cook 2013-08-15 15:27:38 -0700
  • 9b70ecf546 Reg standardization Henry Cook 2013-08-13 17:53:19 -0700
  • 1308c08baa Reg standardization Henry Cook 2013-08-13 17:52:53 -0700
  • b570435847 Reg standardization Henry Cook 2013-08-13 17:50:02 -0700
  • 7ff4126d04 Abstracted UncachedTileLinkIOArbiters Henry Cook 2013-08-13 00:01:11 -0700
  • 9162fbc9b5 Clean up cloning in tilelink bundles Henry Cook 2013-08-12 23:15:54 -0700
  • 858169917e removed dummy DNCs handled by pruning Henry Cook 2013-08-12 22:34:46 -0700
  • d9b3c7cfc8 Moved RenEn to ChiselUtil Henry Cook 2013-08-12 22:18:25 -0700
  • d7d13255db chisel tag Huy Vo 2013-08-12 20:53:29 -0700
  • f9d1403a92 tags Huy Vo 2013-08-12 20:53:17 -0700