fix scr parameterization bug
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2ca5127785
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44e92edf92
@ -113,6 +113,9 @@ class PCR(implicit conf: RocketConfiguration) extends Component
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val rdata = Bits(OUTPUT, conf.xprlen)
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val wdata = Bits(INPUT, conf.xprlen)
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}
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// there is a fixed constant related to this in PCRReq.addr
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require(log2Up(conf.nxpr) == 5)
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val status = new Status().asOutput
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val ptbr = UFix(OUTPUT, PADDR_BITS)
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@ -21,7 +21,7 @@ class HostIO(val w: Int) extends Bundle
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class PCRReq extends Bundle
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{
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val rw = Bool()
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val addr = Bits(width = 6)
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val addr = Bits(width = 5)
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val data = Bits(width = 64)
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}
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@ -237,6 +237,7 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
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}
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}
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val scr_addr = addr(log2Up(nSCR)-1, 0)
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val scr_rdata = Vec(io.scr.rdata.size){Bits(width = 64)}
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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@ -245,10 +246,10 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
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io.scr.wen := false
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io.scr.wdata := pcr_wdata
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io.scr.waddr := pcr_addr.toUFix
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io.scr.waddr := scr_addr.toUFix
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when (state === state_pcr_req && pcr_coreid === Fix(-1)) {
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io.scr.wen := cmd === cmd_writecr
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pcrReadData := scr_rdata(pcr_addr)
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pcrReadData := scr_rdata(scr_addr)
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state := state_tx
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}
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