riscv/rocket-chip
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Adjust ordering of RoCCInstruction to reflect new ISA encoding. (Note: Fixes register op issues with AccumulatorExample but still slight issue with executing memory loads)

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Stephen Twigg 2013-09-22 03:18:06 -07:00
parent 1d2f4f8437
commit 158cee08af
1 changed files with 3 additions and 3 deletions
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6
rocket/src/main/scala/rocc.scala
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@ -6,13 +6,13 @@ import uncore._
class RoCCInstruction extends Bundle
{
val rd = Bits(width = 5)
val rs1 = Bits(width = 5)
val rs2 = Bits(width = 5)
val funct = Bits(width = 7)
val rs2 = Bits(width = 5)
val rs1 = Bits(width = 5)
val xd = Bool()
val xs1 = Bool()
val xs2 = Bool()
val rd = Bits(width = 5)
val opcode = Bits(width = 7)
}