riscv/rocket-chip
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From Andrew, actually mark scoreboard when rocc instruction with a writeback is issued. Also, fix an issue with AccumulatorExample not properly tagging its memory requests. Finally, reverted changes from f27429c to more properly follow the spike model (always return previous value of accumulator).

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This commit is contained in:
Stephen Twigg 2013-09-24 10:54:09 -07:00
parent db1e09f0d0
commit 3532ae0b79
2 changed files with 7 additions and 10 deletions
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2
rocket/src/main/scala/ctrl.scala
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@ -595,7 +595,7 @@ class Control(implicit conf: RocketConfiguration) extends Module
}
val sboard = new Scoreboard(32)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.set((wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val) && io.dpath.wb_wen, io.dpath.wb_waddr)
sboard.clear(io.dpath.mem_ll_wb, io.dpath.mem_ll_waddr)
val id_stall_fpu = if (conf.fpu) {

15
rocket/src/main/scala/rocc.scala
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@ -91,24 +91,21 @@ class AccumulatorExample(conf: RocketConfiguration) extends RoCC(conf)
val stallLoad = doLoad && !io.mem.req.ready
val stallResp = doResp && !io.resp.ready
val loadSent = Reg(init=Bool(false))
when(cmd.fire()) { loadSent := Bool(false) }.elsewhen(io.mem.req.fire()) {loadSent := Bool(true)}
// This ensures that, even if we hold a command at the queue, it is only processed once
cmd.ready := !stallReg && !stallLoad && !stallResp && (!doLoad || !doResp || loadSent)
cmd.ready := !stallReg && !stallLoad && !stallResp
// command resolved if no stalls AND not issuing a load that will need a request
// note, loadSent = true will occur when the load response comes back
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad && (!doLoad || loadSent)
// valid response if valid command, need a response, no stalls on needed reg AND not issuing a load
io.resp.valid := cmd.valid && doResp && !stallReg && !stallLoad
// valid response if valid command, need a response, and no stalls
io.resp.bits.rd := cmd.bits.inst.rd
io.resp.bits.data := accum
io.resp.bits.data := accum // Semantics is to always send out prior accumulator register value
io.busy := Bool(false)
io.interrupt := Bool(false)
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp && !loadSent
io.mem.req.valid := cmd.valid && doLoad && !stallReg && !stallResp
io.mem.req.bits.addr := addend
io.mem.req.bits.tag := addr
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores...