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rocket-chip
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Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.

This commit is contained in:
Stephen Twigg 2013-09-09 14:31:18 -07:00
parent f27c0fb010 2c47b4388a
commit 6cde69e95d
4 changed files with 12 additions and 11 deletions
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2
rocket

@ -1 +1 @@
Subproject commit 875e28f17e6cd227bd77447aadec2fd8e9c264e3
Subproject commit 5aedce69066d748b356d4e17b3e155272988dcc0

15
src/main/scala/RocketChip.scala
View File

@ -17,10 +17,12 @@ object DummyTopLevelConstants {
val HAS_VEC = false
val HAS_FPU = true
val NL2_REL_XACTS = 1
val NL2_ACQ_XACTS = 8
val NL2_ACQ_XACTS = 7
val NMSHRS = 2
}
import DummyTopLevelConstants._
object ReferenceChipBackend {
val initMap = new HashMap[Module, Bool]()
}
@ -91,8 +93,8 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
val llc_tag_leaf = Mem(Bits(width = 152), 512, seqRead = true)
val llc_data_leaf = Mem(Bits(width = 64), 4096, seqRead = true)
val llc = Module(new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf))
//val llc = Module(new DRAMSideLLCNull(8, REFILL_CYCLES))
val llc = Module(new DRAMSideLLC(sets=512, ways=8, outstanding=16, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
//val llc = Module(new DRAMSideLLCNull(NL2_REL_XACTS+NL2_ACQ_XACTS, REFILL_CYCLES))
val mem_serdes = Module(new MemSerdes(htif_width))
require(clientEndpoints.length == ln.nClients)
@ -137,7 +139,7 @@ class OuterMemorySystem(htif_width: Int, clientEndpoints: Seq[ClientCoherenceAge
io.mem_backup <> mem_serdes.io.narrow
}
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int)
case class UncoreConfiguration(l2: L2CoherenceAgentConfiguration, tl: TileLinkConfiguration, nTiles: Int, nBanks: Int, bankIdLsb: Int, nSCR: Int)
class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf: UncoreConfiguration) extends Module
{
@ -152,7 +154,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
}
val htif = Module(new RocketHTIF(htif_width))
val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
@ -223,7 +225,6 @@ class VLSITopIO(htifWidth: Int) extends TopIO(htifWidth) {
val out_mem_valid = Bool(OUTPUT)
}
import DummyTopLevelConstants._
class MemDessert extends Module {
val io = new MemDesserIO(HTIF_WIDTH)
@ -244,7 +245,7 @@ class Top extends Module {
implicit val ln = LogicalNetworkConfiguration(NTILES+NBANKS+1, log2Up(NTILES)+1, NBANKS, NTILES+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(NL2_REL_XACTS+NL2_ACQ_XACTS), 2*log2Up(NMSHRS*NTILES+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, NL2_REL_XACTS, NL2_ACQ_XACTS)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5)
implicit val uc = UncoreConfiguration(l2, tl, NTILES, NBANKS, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(128, 2, ntlb = 8, nbtb = 16)
val dc = DCacheConfig(128, 4, ntlb = 8,

4
src/main/scala/fpga.scala
View File

@ -46,7 +46,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
}
val htif = Module(new RocketHTIF(htif_width))
val htif = Module(new RocketHTIF(htif_width, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif
@ -89,7 +89,7 @@ class FPGATop extends Module {
implicit val ln = LogicalNetworkConfiguration(ntiles+nbanks+1, log2Up(ntiles)+1, nbanks, ntiles+1)
implicit val tl = TileLinkConfiguration(co, ln, log2Up(1+8), 2*log2Up(nmshrs*ntiles+1), MEM_DATA_BITS)
implicit val l2 = L2CoherenceAgentConfiguration(tl, 1, 8)
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5)
implicit val uc = UncoreConfiguration(l2, tl, ntiles, nbanks, bankIdLsb = 5, nSCR = 64)
val ic = ICacheConfig(64, 1, ntlb = 4, nbtb = 4)
val dc = DCacheConfig(64, 1, ntlb = 4, nmshr = 2, nrpq = 16, nsdq = 17, states = co.nClientStates)

2
uncore

@ -1 +1 @@
Subproject commit 4a8bb15978e2563aabbe41ec8797c5abbdaaf216
Subproject commit 8cc795712b5e6e38dc494bbd56d62abdb04668be