Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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d4a0db4575
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@ -37,6 +37,8 @@ class CtrlDpathIO extends Bundle()
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val ex_mem_type = Bits(OUTPUT, 3)
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val ex_rs2_val = Bool(OUTPUT)
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val mem_rs2_val = Bool(OUTPUT)
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val mem_ll_bypass_rs1 = Bool(OUTPUT)
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val mem_ll_bypass_rs2 = Bool(OUTPUT)
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// exception handling
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val exception = Bool(OUTPUT);
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val cause = UInt(OUTPUT, 6);
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@ -605,11 +607,17 @@ class Control(implicit conf: RocketConfiguration) extends Module
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class Scoreboard(n: Int)
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{
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val r = Reg(init=Bits(0, n))
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var _next = r
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private var _next = r
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private var cur = r
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var ens = Bool(false)
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def apply(addr: UInt) = r(addr)
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def set(en: Bool, addr: UInt): Unit = update(en, _next | mask(en, addr))
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def clear(en: Bool, addr: UInt): Unit = update(en, _next & ~mask(en, addr))
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def clear(en: Bool, addr: UInt): Unit = {
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val m = ~mask(en, addr)
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update(en, _next & m)
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//cur = cur & m
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}
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def read(addr: UInt) = r(addr)
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def readBypassed(addr: UInt) = cur(addr)
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private def mask(en: Bool, addr: UInt) = Mux(en, UInt(1) << addr, UInt(0))
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private def update(en: Bool, update: UInt) = {
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_next = update
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@ -628,10 +636,10 @@ class Control(implicit conf: RocketConfiguration) extends Module
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fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra)
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fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra)
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io.fpu.dec.ren1 && fp_sboard(id_raddr1) ||
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io.fpu.dec.ren2 && fp_sboard(id_raddr2) ||
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io.fpu.dec.ren3 && fp_sboard(id_raddr3) ||
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io.fpu.dec.wen && fp_sboard(id_waddr)
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io.fpu.dec.ren1 && fp_sboard.readBypassed(id_raddr1) ||
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io.fpu.dec.ren2 && fp_sboard.readBypassed(id_raddr2) ||
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io.fpu.dec.ren3 && fp_sboard.readBypassed(id_raddr3) ||
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io.fpu.dec.wen && fp_sboard.readBypassed(id_waddr)
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} else Bool(false)
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// write cause to PCR on an exception
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@ -699,10 +707,12 @@ class Control(implicit conf: RocketConfiguration) extends Module
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val id_wb_hazard = data_hazard_wb && (wb_dcache_miss || wb_reg_div_mul_val) ||
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fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val)
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io.dpath.mem_ll_bypass_rs1 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr1
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io.dpath.mem_ll_bypass_rs2 := io.dpath.mem_ll_wb && io.dpath.mem_ll_waddr === id_raddr2
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val id_sboard_hazard =
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(id_raddr1 != UInt(0) && id_renx1 && sboard(id_raddr1) ||
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id_raddr2 != UInt(0) && id_renx2 && sboard(id_raddr2) ||
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id_waddr != UInt(0) && id_wen && sboard(id_waddr))
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(id_raddr1 != UInt(0) && id_renx1 && sboard.read(id_raddr1) && !io.dpath.mem_ll_bypass_rs1 ||
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id_raddr2 != UInt(0) && id_renx2 && sboard.read(id_raddr2) && !io.dpath.mem_ll_bypass_rs2 ||
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id_waddr != UInt(0) && id_wen && sboard.read(id_waddr))
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val ctrl_stalld =
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id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard ||
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@ -71,22 +71,17 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
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// bypass muxes
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val id_rs1_zero = id_raddr1 === UInt(0)
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val id_rs1_ex_bypass = io.ctrl.ex_wen && id_raddr1 === ex_reg_waddr
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr
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val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass
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val id_rs1_bypass_src = Mux(id_rs1_zero, UInt(0), Mux(id_rs1_ex_bypass, UInt(1), UInt(2) | io.ctrl.mem_load))
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val id_rs1 =
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Mux(id_raddr1 === UInt(0), UInt(0),
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Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr1)))
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val id_rs1_mem_bypass = io.ctrl.mem_wen && id_raddr1 === mem_reg_waddr
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val id_rs1_bypass = id_rs1_zero || id_rs1_ex_bypass || id_rs1_mem_bypass || io.ctrl.mem_ll_bypass_rs1
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val id_rs1_bypass_src = Mux(id_rs1_zero, UInt(0), Mux(id_rs1_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
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val id_rs1 = Mux(wb_wen && id_raddr1 === wb_reg_waddr, wb_wdata, readRF(id_raddr1))
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val id_rs2_zero = id_raddr2 === UInt(0)
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val id_rs2_ex_bypass = io.ctrl.ex_wen && id_raddr2 === ex_reg_waddr
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val id_rs2_mem_bypass = io.ctrl.mem_wen && id_raddr2 === mem_reg_waddr
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val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass
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val id_rs2_bypass_src = Mux(id_rs2_zero, UInt(0), Mux(id_rs2_ex_bypass, UInt(1), UInt(2) | io.ctrl.mem_load))
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val id_rs2 = Mux(id_raddr2 === UInt(0), UInt(0),
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Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata,
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readRF(id_raddr2)))
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val id_rs2_bypass = id_rs2_zero || id_rs2_ex_bypass || id_rs2_mem_bypass || io.ctrl.mem_ll_bypass_rs2
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val id_rs2_bypass_src = Mux(id_rs2_zero, UInt(0), Mux(id_rs2_ex_bypass, UInt(1), Mux(io.ctrl.mem_load, UInt(3), UInt(2))))
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val id_rs2 = Mux(wb_wen && id_raddr2 === wb_reg_waddr, wb_wdata, readRF(id_raddr2))
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// immediate generation
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def imm(sel: Bits, inst: Bits) = {
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@ -120,7 +120,7 @@ class TLB(entries: Int) extends Module
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val sx_array = Reg(Bits()) // supervisor execute permission
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when (io.ptw.resp.valid) {
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tag_ram(r_refill_waddr) := io.ptw.resp.bits.ppn
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val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm(5,0)
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val perm = (!io.ptw.resp.bits.error).toSInt & io.ptw.resp.bits.perm
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ur_array := ur_array.bitSet(r_refill_waddr, perm(0))
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uw_array := uw_array.bitSet(r_refill_waddr, perm(1))
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ux_array := ux_array.bitSet(r_refill_waddr, perm(2))
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