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fix memserdes bit ordering

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This commit is contained in:
Yunsup Lee 2013-08-24 15:24:17 -07:00
parent bc2b45da12
commit b01fe4f6aa
1 changed files with 1 additions and 2 deletions
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3
uncore/src/memserdes.scala
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@ -107,8 +107,7 @@ class MemSerdes(w: Int) extends Component
}
io.wide.resp.valid := resp_val
io.wide.resp.bits.tag := in_buf(io.wide.resp.bits.tag.width-1,0)
io.wide.resp.bits.data := in_buf >> UFix(io.wide.resp.bits.tag.width)
io.wide.resp.bits := io.wide.resp.bits.fromBits(in_buf)
}
class MemDesserIO(w: Int) extends Bundle {