Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes

.gitmodules

@@ -1,12 +1,3 @@
-[submodule "hardfloat"]
-	path = hardfloat
-	url = git@github.com:ucb-bar/hardfloat.git
-[submodule "chisel"]
-	path = chisel
-	url = git@github.com:ucb-bar/chisel.git
-[submodule "riscv-rocket"]
-	path = riscv-rocket
-	url = git@github.com:ucb-bar/riscv-rocket.git
 [submodule "uncore"]
 	path = uncore
 	url = git@github.com:ucb-bar/uncore.git
@@ -16,3 +7,6 @@
 [submodule "riscv-tools"]
 	path = riscv-tools
 	url = git@github.com:ucb-bar/riscv-tools.git
+[submodule "rocket"]
+	path = rocket
+	url = git@github.com:ucb-bar/riscv-rocket.git

Makefrag

@@ -12,6 +12,8 @@ $(DRAMSIM_OBJS): %.o: %.cpp
 $(sim_dir)/libdramsim.a: $(DRAMSIM_OBJS)
 	ar rcs $@ $^
 
+src_path = src/main/scala
+
 #--------------------------------------------------------------------
 # Tests
 #--------------------------------------------------------------------

chisel

@@ -1 +0,0 @@
-Subproject commit 8eb2d8a20d97722f4b5f40ab74eb19c8585d690f

emulator/Makefile

@@ -8,21 +8,21 @@ include $(base_dir)/Makefrag
 CXXFLAGS := $(CXXFLAGS) -std=c++11 -I$(RISCV)/include
 
 CXXSRCS := emulator disasm mm mm_dramsim2
-CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/chisel/csrc -I$(base_dir)/dramsim2
+CXXFLAGS := $(CXXFLAGS) -I$(base_dir)/csrc -I$(base_dir)/dramsim2
 
 LDFLAGS := $(LDFLAGS) -L$(RISCV)/lib -L. -ldramsim -lfesvr -lpthread
 
 OBJS := $(addsuffix .o,$(CXXSRCS) $(MODEL))
 DEBUG_OBJS := $(addsuffix -debug.o,$(CXXSRCS) $(MODEL))
 
-CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir $(base_dir)/emulator/generated-src
+CHISEL_ARGS := $(MODEL) --noIoDebug --backend c --targetDir emulator/generated-src
 CHISEL_ARGS_DEBUG := $(CHISEL_ARGS)-debug --debug --vcd --ioDebug
 
-generated-src/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/main/scala/*.scala $(base_dir)/src/*.scala
-	cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS)"
+generated-src/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
+	cd $(base_dir) && $(SBT) "elaborate $(CHISEL_ARGS)"
 
-generated-src-debug/$(MODEL).cpp: $(base_dir)/riscv-rocket/src/*.scala $(base_dir)/riscv-hwacha/src/*.scala $(base_dir)/chisel/src/main/scala/* $(base_dir)/uncore/src/main/*.scala $(base_dir)/src/*.scala
-	cd $(base_dir)/sbt && $(SBT) "project referencechip" "elaborate $(CHISEL_ARGS_DEBUG)"
+generated-src-debug/$(MODEL).cpp: $(base_dir)/rocket/$(src_path)/*.scala $(base_dir)/hwacha/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala $(base_dir)/$(src_path)/*.scala
+	cd $(base_dir) && $(SBT) "elaborate $(CHISEL_ARGS_DEBUG)"
 
 $(MODEL).o: %.o: generated-src/%.cpp
 	$(CXX) $(CXXFLAGS) -Igenerated-src -c -o $@ $<
@@ -46,7 +46,7 @@ clean:
 	rm -rf *.o *.a emulator emulator-debug generated-src generated-src-debug DVEfiles output
 
 test:
-	cd $(base_dir)/sbt && $(SBT) "project referencechip" "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
+	cd $(base_dir) && $(SBT) "~make $(CURDIR) run-fast $(CHISEL_ARGS)"
 
 #--------------------------------------------------------------------
 # Run assembly tests and benchmarks

hardfloat

@@ -1 +0,0 @@
-Subproject commit 76ac1cb932949dc33a11dd85f9bf9cbc3a639eb4

project/build.scala

@@ -15,15 +15,15 @@ object BuildSettings extends Build {
     scalaVersion := buildScalaVersion,
     traceLevel   := 15,
     scalacOptions ++= Seq("-deprecation","-unchecked"),
-    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value
+    libraryDependencies ++= Seq("org.scala-lang" % "scala-reflect" % scalaVersion.value,
+                            "edu.berkeley.cs" %% "chisel" % "2.1-SNAPSHOT",
+                            "edu.berkeley.cs" %% "hardfloat" % "1.2")
   )
 
-  lazy val chisel = Project("chisel", file("chisel"), settings = buildSettings)
-  lazy val hardfloat = Project("hardfloat", file("hardfloat"), settings = buildSettings) dependsOn(chisel)
-  lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings) dependsOn(hardfloat,chisel)
-  lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings) dependsOn(chisel)
-  lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha,hardfloat,chisel)
-  lazy val referencechip = Project("referencechip", file("referencechip"), settings = buildSettings ++ chipSettings) dependsOn(chisel,rocket)
+  lazy val hwacha = Project("hwacha", file("hwacha"), settings = buildSettings)
+  lazy val uncore = Project("uncore", file("uncore"), settings = buildSettings)
+  lazy val rocket = Project("rocket", file("rocket"), settings = buildSettings) dependsOn(uncore,hwacha)
+  lazy val referencechip = Project("referencechip", file("."), settings = buildSettings ++ chipSettings) dependsOn(rocket)
 
   val elaborateTask = InputKey[Unit]("elaborate", "convert chisel components into backend source code")
   val makeTask = InputKey[Unit]("make", "trigger backend-specific makefile command")

riscv-rocket

@@ -1 +0,0 @@
-Subproject commit 4461c5f4ed3e3f8192c7497e2431ccf1a7ff12cb

rocket

@@ -0,0 +1 @@
+Subproject commit 875e28f17e6cd227bd77447aadec2fd8e9c264e3

src/main/scala/fpga.scala

@@ -48,6 +48,8 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
   }
   val htif = Module(new RocketHTIF(htif_width))
   val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
+  val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
+  outmemsys.io.incoherent := incoherentWithHtif
   htif.io.cpu <> io.htif
   outmemsys.io.mem <> io.mem
 
@@ -57,7 +59,6 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
     addr(conf.bankIdLsb + log2Up(conf.nBanks) - 1, conf.bankIdLsb)
   }
 
-  outmemsys.io.incoherent <> (io.incoherent :+ Bool(true))
   (outmemsys.io.tiles :+ outmemsys.io.htif).zip(io.tiles :+ htif.io.mem).zipWithIndex.map { 
     case ((outer, client), i) => 
       outer.acquire <> TileLinkHeaderAppender(client.acquire, i, conf.nBanks, convertAddrToBank _)
@@ -138,7 +139,7 @@ abstract class AXISlave extends Module {
 
 class Slave extends AXISlave
 {
-  val top = new FPGATop
+  val top = Module(new FPGATop)
 
   val memw = top.io.mem.resp.bits.data.getWidth
   val htifw = top.io.host.in.bits.getWidth

src/main/scala/network.scala

@@ -109,7 +109,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
   // Shims for converting between logical network IOs and physical network IOs
   //TODO: Could be less verbose if you could override subbundles after a <>
   def DefaultFromCrossbarShim[T <: Data](in: FBCIO[T]): FLNIO[T] = {
-    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone))
+    val out = Decoupled(new LogicalNetworkIO()(in.bits.payload.clone)).asDirectionless
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid
@@ -127,7 +127,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgentRole])(implicit
     out
   }
   def DefaultToCrossbarShim[T <: Data](in: FLNIO[T]): FBCIO[T] = {
-    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone))
+    val out = Decoupled(new PhysicalNetworkIO()(in.bits.payload.clone)).asDirectionless
     out.bits.header := in.bits.header
     out.bits.payload := in.bits.payload
     out.valid := in.valid