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Clean up cloning in tilelink bundles

This commit is contained in:
Henry Cook 2013-08-12 23:15:54 -07:00
parent 5c7a1f5cd6
commit 9162fbc9b5

View File

@ -5,7 +5,7 @@ case class TileLinkConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNet
abstract trait TileLinkSubBundle extends Bundle {
implicit val conf: TileLinkConfiguration
// TODO: override clone here, passing conf
override def clone = this.getClass.getConstructors.head.newInstance(conf).asInstanceOf[this.type]
}
trait HasPhysicalAddress extends TileLinkSubBundle {
@ -30,7 +30,7 @@ trait MasterSourcedMessage extends SourcedMessage
object Acquire
{
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt)(implicit conf: TileLinkConfiguration) = {
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt)(implicit conf: TileLinkConfiguration): Acquire = {
val acq = new Acquire
acq.a_type := a_type
acq.addr := addr
@ -40,24 +40,15 @@ object Acquire
acq.atomic_opcode := Bits(0)
acq
}
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, write_mask: Bits)(implicit conf: TileLinkConfiguration) = {
val acq = new Acquire
acq.a_type := a_type
acq.addr := addr
acq.client_xact_id := client_xact_id
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, write_mask: Bits)(implicit conf: TileLinkConfiguration): Acquire = {
val acq = apply(a_type, addr, client_xact_id)
acq.write_mask := write_mask
acq.subword_addr := Bits(0)
acq.atomic_opcode := Bits(0)
acq
}
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, subword_addr: UInt, atomic_opcode: UInt)(implicit conf: TileLinkConfiguration) = {
val acq = new Acquire
acq.a_type := a_type
acq.addr := addr
acq.client_xact_id := client_xact_id
def apply(a_type: Bits, addr: UInt, client_xact_id: UInt, subword_addr: UInt, atomic_opcode: UInt)(implicit conf: TileLinkConfiguration): Acquire = {
val acq = apply(a_type, addr, client_xact_id)
acq.subword_addr := subword_addr
acq.atomic_opcode := atomic_opcode
acq.write_mask := Bits(0)
acq
}
}
@ -66,17 +57,12 @@ class Acquire(implicit val conf: TileLinkConfiguration) extends ClientSourcedMes
val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS)
val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS)
val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS)
override def clone = { (new Acquire).asInstanceOf[this.type] }
}
class AcquireData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData {
override def clone = { (new AcquireData).asInstanceOf[this.type] }
}
class AcquireData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData
class Probe(implicit val conf: TileLinkConfiguration) extends MasterSourcedMessage with HasPhysicalAddress with HasMasterTransactionId {
val p_type = Bits(width = conf.co.probeTypeWidth)
override def clone = { (new Probe).asInstanceOf[this.type] }
}
object Release
@ -92,22 +78,15 @@ object Release
}
class Release(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId with HasMasterTransactionId {
val r_type = Bits(width = conf.co.releaseTypeWidth)
override def clone = { (new Release).asInstanceOf[this.type] }
}
class ReleaseData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData {
override def clone = { (new ReleaseData).asInstanceOf[this.type] }
}
class ReleaseData(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasTileLinkData
class Grant(implicit val conf: TileLinkConfiguration) extends MasterSourcedMessage with HasTileLinkData with HasClientTransactionId with HasMasterTransactionId {
val g_type = Bits(width = conf.co.grantTypeWidth)
override def clone = { (new Grant).asInstanceOf[this.type] }
}
class GrantAck(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId {
override def clone = { (new GrantAck).asInstanceOf[this.type] }
}
class GrantAck(implicit val conf: TileLinkConfiguration) extends ClientSourcedMessage with HasMasterTransactionId
trait DirectionalIO
trait ClientSourcedIO extends DirectionalIO