Reg standardization

uncore/src/llc.scala

@@ -370,7 +370,7 @@ class DRAMSideLLC(sets: Int, ways: Int, outstanding: Int, tagLeaf: Mem[UInt], da
   val s3_rdy = Bool()
   val replay_s2_rdy = Bool()
 
-  val s1_valid = Reg(update = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, reset = Bool(false))
+  val s1_valid = Reg(updateData = io.cpu.req_cmd.fire() || replay_s2 && replay_s2_rdy, resetData = Bool(false))
   val s1 = Reg(new MemReqCmd)
   when (io.cpu.req_cmd.fire()) { s1 := io.cpu.req_cmd.bits }
   when (replay_s2 && replay_s2_rdy) { s1 := s2 }

uncore/src/network.scala

@@ -148,43 +148,25 @@ class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle {
 
 object FIFOedLogicalNetworkIOWrapper {
   def apply[T <: Data](in: DecoupledIO[T], src: UInt = UInt(0), dst: UInt = UInt(0))(implicit conf: LogicalNetworkConfiguration) = {
-    val shim = Module((new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone })
-    shim.io.in.valid := in.valid
-    shim.io.in.bits := in.bits
-    in.ready := shim.io.in.ready
-    shim.io.out
+    val out = Decoupled((new LogicalNetworkIO){in.bits.clone}).asDirectionless
+    out.valid := in.valid
+    out.bits.payload := in.bits
+    out.bits.header.dst := dst
+    out.bits.header.src := src
+    in.ready := out.ready
+    out
   }
 }
-class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UInt, dst: UInt)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Module {
-  val io = new Bundle {
-    val in = Decoupled(data).flip
-    val out = Decoupled((new LogicalNetworkIO){data})
-  }
-  io.out.valid := io.in.valid
-  io.out.bits.payload := io.in.bits
-  io.out.bits.header.dst := dst
-  io.out.bits.header.src := src
-  io.in.ready := io.out.ready
-}
 
 object FIFOedLogicalNetworkIOUnwrapper {
   def apply[T <: Data](in: DecoupledIO[LogicalNetworkIO[T]])(implicit conf: LogicalNetworkConfiguration) = {
-    val shim = Module((new FIFOedLogicalNetworkIOUnwrapper){ in.bits.payload.clone })
-    shim.io.in.valid := in.valid
-    shim.io.in.bits := in.bits
-    in.ready := shim.io.in.ready
-    shim.io.out
+    val out = Decoupled(in.bits.payload.clone).asDirectionless
+    out.valid := in.valid
+    out.bits := in.bits.payload
+    in.ready := out.ready
+    out
   }
 }
-class FIFOedLogicalNetworkIOUnwrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Module {
-  val io = new Bundle {
-    val in = Decoupled((new LogicalNetworkIO){data}).flip
-    val out = Decoupled(data)
-  }
-  io.out.valid := io.in.valid
-  io.out.bits := io.in.bits.payload
-  io.in.ready := io.out.ready
-}
 
 class LogicalNetworkIO[T <: Data]()(data: => T)(implicit conf: LogicalNetworkConfiguration) extends Bundle {
   val header = new LogicalHeader

uncore/src/slowio.scala

@@ -47,7 +47,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
   val out_slow_bits = Reg(data)
 
   val fromhost_q = Module(new Queue(data,1))
-  fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || this.getReset)
+  fromhost_q.io.enq.valid := rising && (io.in_slow.valid && in_slow_rdy || reset)
   fromhost_q.io.enq.bits := io.in_slow.bits
   fromhost_q.io.deq <> io.in_fast
 
@@ -58,7 +58,7 @@ class SlowIO[T <: Data](val divisor_max: Int)(data: => T) extends Module
   when (held) {
     in_slow_rdy := fromhost_q.io.enq.ready
     out_slow_val := tohost_q.io.deq.valid
-    out_slow_bits := Mux(this.getReset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
+    out_slow_bits := Mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
   }
 
   io.in_slow.ready := in_slow_rdy