Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
Conflicts: chisel riscv-hwacha riscv-rocket uncore
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2
chisel
2
chisel
Submodule chisel updated: 58cb89a883...8eb2d8a20d
Submodule riscv-rocket updated: 744846b72e...4461c5f4ed
@ -14,7 +14,7 @@ object DummyTopLevelConstants {
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val HTIF_WIDTH = 16
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val ENABLE_SHARING = true
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val ENABLE_CLEAN_EXCLUSIVE = true
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val HAS_VEC = true
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val HAS_VEC = false
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val HAS_FPU = true
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val NL2_REL_XACTS = 1
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val NL2_ACQ_XACTS = 8
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uncore
2
uncore
Submodule uncore updated: 113ba96c49...4a8bb15978
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