Merge branch 'master' into chisel-v2
Conflicts: src/main/scala/htif.scala
This commit is contained in:
commit
d896ccbd43
@ -117,6 +117,9 @@ class PCR(implicit conf: RocketConfiguration) extends Module
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val rdata = Bits(OUTPUT, conf.xprlen)
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val wdata = Bits(INPUT, conf.xprlen)
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}
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// there is a fixed constant related to this in PCRReq.addr
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require(log2Up(conf.nxpr) == 5)
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val status = new Status().asOutput
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val ptbr = UInt(OUTPUT, PADDR_BITS)
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@ -16,7 +16,7 @@ class HostIO(val w: Int) extends Bundle
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class PCRReq extends Bundle
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{
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val rw = Bool()
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val addr = Bits(width = 6)
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val addr = Bits(width = 5)
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val data = Bits(width = 64)
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}
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@ -30,7 +30,7 @@ class HTIFIO(ntiles: Int) extends Bundle
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val ipi_rep = Decoupled(Bool()).flip
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}
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class SCRIO extends Bundle
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class SCRIO(n: Int) extends Bundle
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{
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val n = 64
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val rdata = Vec.fill(n){Bits(INPUT, 64)}
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@ -39,7 +39,7 @@ class SCRIO extends Bundle
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val wdata = Bits(OUTPUT, 64)
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}
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class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module with ClientCoherenceAgent
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class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extends Component with ClientCoherenceAgent
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{
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implicit val (ln, co) = (conf.ln, conf.co)
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val nTiles = ln.nClients-1 // This HTIF is itself a TileLink client
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@ -47,7 +47,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
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val host = new HostIO(w)
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val cpu = Vec.fill(nTiles){new HTIFIO(nTiles).flip}
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val mem = new TileLinkIO
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val scr = new SCRIO
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val scr = new SCRIO(nSCR)
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}
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val short_request_bits = 64
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@ -233,6 +233,7 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
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}
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}
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val scr_addr = addr(log2Up(nSCR)-1, 0)
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val scr_rdata = Vec.fill(io.scr.rdata.size){Bits(width = 64)}
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for (i <- 0 until scr_rdata.size)
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scr_rdata(i) := io.scr.rdata(i)
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@ -241,10 +242,10 @@ class RocketHTIF(w: Int)(implicit conf: TileLinkConfiguration) extends Module wi
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io.scr.wen := false
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io.scr.wdata := pcr_wdata
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io.scr.waddr := pcr_addr.toUInt
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io.scr.waddr := scr_addr.toUInt
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when (state === state_pcr_req && pcr_coreid === SInt(-1)) {
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io.scr.wen := cmd === cmd_writecr
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pcrReadData := scr_rdata(pcr_addr)
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pcrReadData := scr_rdata(scr_addr)
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state := state_tx
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}
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