Export stats pcr register (#28 currently) to the top-level
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@ -133,7 +133,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
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val irq_timer = Bool(OUTPUT)
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val irq_ipi = Bool(OUTPUT)
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val replay = Bool(OUTPUT)
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val stats = Bool(OUTPUT)
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}
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import PCR._
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@ -171,6 +170,8 @@ class PCR(implicit conf: RocketConfiguration) extends Module
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host_pcr_bits.data := io.rw.rdata
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}
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when (io.host.pcr_rep.fire()) { host_pcr_rep_valid := false }
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io.host.debug_stats_pcr := reg_stats // direct export up the hierarchy
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val addr = Mux(io.rw.cmd != PCR.N, io.rw.addr, host_pcr_bits.addr)
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val wen = io.rw.cmd === PCR.T || io.rw.cmd === PCR.S || io.rw.cmd === PCR.C ||
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@ -183,7 +184,6 @@ class PCR(implicit conf: RocketConfiguration) extends Module
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io.fatc := wen && addr === FATC
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io.evec := Mux(io.exception, reg_evec.toSInt, reg_epc).toUInt
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io.ptbr := reg_ptbr
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io.stats := reg_stats
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when (io.badvaddr_wen) {
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val wdata = io.rw.wdata
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@ -11,6 +11,7 @@ class HostIO(val w: Int) extends Bundle
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val clk_edge = Bool(OUTPUT)
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val in = Decoupled(Bits(width = w)).flip
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val out = Decoupled(Bits(width = w))
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val debug_stats_pcr = Bool(OUTPUT)
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}
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class PCRReq extends Bundle
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@ -28,6 +29,9 @@ class HTIFIO(ntiles: Int) extends Bundle
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val pcr_rep = Decoupled(Bits(width = 64))
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val ipi_req = Decoupled(Bits(width = log2Up(ntiles)))
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val ipi_rep = Decoupled(Bool()).flip
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val debug_stats_pcr = Bool(OUTPUT)
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// wired directly to stats register
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// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
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}
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class SCRIO(n: Int) extends Bundle
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@ -49,6 +53,9 @@ class RocketHTIF(w: Int, nSCR: Int)(implicit conf: TileLinkConfiguration) extend
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val scr = new SCRIO(nSCR)
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}
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io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
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// system is 'interesting' if any tile is 'interesting'
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val short_request_bits = 64
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val long_request_bits = 576
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require(short_request_bits % w == 0)
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