riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

don't disassemble within chisel

Browse Source
This commit is contained in:
Andrew Waterman
2013-09-15 04:14:45 -07:00
parent f12bbc1e43
commit 88d1c47665
2 changed files with 2 additions and 267 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
rocket/src/main/scala/dpath.scala
View File

@@ -317,10 +317,10 @@ class Datapath(implicit conf: RocketConfiguration) extends Module
Mux(io.ctrl.sel_pc === PC_PCR, pcr.io.evec,
wb_reg_pc)).toUInt // PC_WB
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] %s\n",
printf("C: %d [%d] pc=[%x] W[r%d=%x] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
tsc_reg(32,0), io.ctrl.wb_valid, wb_reg_pc,
Mux(wb_wen, wb_reg_waddr, UInt(0)), wb_wdata,
wb_reg_inst(26,22), Reg(next=Reg(next=ex_rs1)),
wb_reg_inst(21,17), Reg(next=Reg(next=ex_rs2)),
wb_reg_inst, Disassemble(wb_reg_inst))
wb_reg_inst, wb_reg_inst)
}

265
rocket/src/main/scala/instructions.scala
View File

@@ -192,268 +192,3 @@ object Instructions
def CUSTOM3_RD_RS1 = Bits("b??????????????????????1101111011")
def CUSTOM3_RD_RS1_RS2 = Bits("b??????????????????????1111111011")
}
object Disassemble
{
def apply(insn: UInt) = {
val name :: fmt :: Nil = ListLookup(insn, default, table)
sprintf("%s %s", name, operands(insn, fmt))
}
private def operands(insn: Bits, fmt: Bits): Bits = {
val x = AVec(Str(" x0"), Str(" ra"), Str(" s0"), Str(" s1"),
Str(" s2"), Str(" s3"), Str(" s4"), Str(" s5"),
Str(" s6"), Str(" s7"), Str(" s8"), Str(" s9"),
Str("s10"), Str("s11"), Str(" sp"), Str(" tp"),
Str(" v0"), Str(" v1"), Str(" a0"), Str(" a1"),
Str(" a2"), Str(" a3"), Str(" a4"), Str(" a5"),
Str(" a6"), Str(" a7"), Str(" t0"), Str(" t1"),
Str(" t2"), Str(" t3"), Str(" t4"), Str(" t5"))
val f = AVec(Str(" fs0"), Str(" fs1"), Str(" fs2"), Str(" fs3"),
Str(" fs4"), Str(" fs5"), Str(" fs6"), Str(" fs7"),
Str(" fs8"), Str(" fs9"), Str("fs10"), Str("fs11"),
Str("fs12"), Str("fs13"), Str("fs14"), Str("fs15"),
Str(" fv0"), Str(" fv1"), Str(" fa0"), Str(" fa1"),
Str(" fa2"), Str(" fa3"), Str(" fa4"), Str(" fa5"),
Str(" fa6"), Str(" fa7"), Str(" ft0"), Str(" ft1"),
Str(" ft2"), Str(" ft3"), Str(" ft4"), Str(" ft5"))
def hex(x: SInt, plus: Char = ' ') =
Cat(Mux(x < SInt(0), Str("-0x"), Str(plus + "0x")), Str(x.abs, 16))
val comma = Str(',')
val lparen = Str('(')
val rparen = Str(')')
val rd = insn(31,27)
val rs1 = insn(26,22)
val rs2 = insn(21,17)
val rs3 = insn(16,12)
val immv = insn(21,10).toSInt
val bmmv = Cat(insn(31,27), insn(16,10)).toSInt
val jmmv = insn(31,7).toSInt
val imm = hex(Mux(fmt === FMT_B, bmmv << UInt(1),
Mux(fmt === FMT_I || fmt === FMT_LD || fmt === FMT_FLD, immv,
Mux(fmt === FMT_ST || fmt === FMT_FST, bmmv,
SInt(0)))))
val jmm = hex(jmmv << UInt(1))
val lmm = Cat(Str("0x"), Str(insn(26,7).toUInt, 16))
val addr = Cat(comma, imm, lparen, x(rs1), rparen)
val r0 = x(rd)
val r1 = Cat(r0, comma, x(rs1))
val r2 = Cat(r1, comma, x(rs2))
val f1 = Cat(f(rd), comma, f(rs1))
val f2 = Cat(f1, comma, f(rs2))
val f3 = Cat(f2, comma, f(rs3))
val fx = Cat(f(rd), comma, x(rs1))
val xf1 = Cat(x(rd), comma, f(rs1))
val xf2 = Cat(xf1, comma, f(rs2))
val z = Str(' ')
val i = Cat(r1, comma, imm)
val b = Cat(x(rs1), comma, x(rs2), comma, imm)
val j = jmm
val l = Cat(x(rd), comma, lmm)
val ld = Cat(x(rd), addr)
val st = Cat(x(rs2), addr)
val fld = Cat(f(rd), addr)
val fst = Cat(f(rs2), addr)
val amo = r2
val opts = Seq(r0, r1, r2, f1, f2, f3, fx, xf1, xf2, z, i, b, j, l, ld, st,
fld, fst, amo)
val maxLen = opts.map(_.getWidth).reduce(_ max _)
val padded = opts.map(x => x.toUInt << UInt(maxLen - x.getWidth))
AVec(padded)(fmt.toUInt)
}
private def FMT_X = Bits("b?????", 5)
private def FMT_R0 = Bits(0, 5)
private def FMT_R1 = Bits(1, 5)
private def FMT_R2 = Bits(2, 5)
private def FMT_F1 = Bits(3, 5)
private def FMT_F2 = Bits(4, 5)
private def FMT_F3 = Bits(5, 5)
private def FMT_FX = Bits(6, 5)
private def FMT_XF1 = Bits(7, 5)
private def FMT_XF2 = Bits(8, 5)
private def FMT_0 = Bits(9, 5)
private def FMT_I = Bits(10, 5)
private def FMT_B = Bits(11, 5)
private def FMT_J = Bits(12, 5)
private def FMT_L = Bits(13, 5)
private def FMT_LD = Bits(14, 5)
private def FMT_ST = Bits(15, 5)
private def FMT_FLD = Bits(16, 5)
private def FMT_FST = Bits(17, 5)
private def FMT_AMO = Bits(18, 5)
private def default = List(Str("unknown "), FMT_0)
import Instructions._
private def table = Array(
BNE-> List(Str("bne "), FMT_B),
BEQ-> List(Str("beq "), FMT_B),
BLT-> List(Str("blt "), FMT_B),
BLTU-> List(Str("bltu "), FMT_B),
BGE-> List(Str("bge "), FMT_B),
BGEU-> List(Str("bgeu "), FMT_B),
JAL-> List(Str("jal "), FMT_J),
JALR-> List(Str("jalr "), FMT_LD),
AUIPC-> List(Str("auipc "), FMT_L),
LB-> List(Str("lb "), FMT_LD),
LH-> List(Str("lh "), FMT_LD),
LW-> List(Str("lw "), FMT_LD),
LD-> List(Str("ld "), FMT_LD),
LBU-> List(Str("lbu "), FMT_LD),
LHU-> List(Str("lhu "), FMT_LD),
LWU-> List(Str("lwu "), FMT_LD),
SB-> List(Str("sb "), FMT_ST),
SH-> List(Str("sh "), FMT_ST),
SW-> List(Str("sw "), FMT_ST),
SD-> List(Str("sd "), FMT_ST),
AMOADD_W-> List(Str("amoaddw "), FMT_AMO),
AMOSWAP_W-> List(Str("amoswapw"), FMT_AMO),
AMOAND_W-> List(Str("amoandw "), FMT_AMO),
AMOOR_W-> List(Str("amoorw "), FMT_AMO),
AMOMIN_W-> List(Str("amominw "), FMT_AMO),
AMOMINU_W-> List(Str("amominuw"), FMT_AMO),
AMOMAX_W-> List(Str("amomaxw "), FMT_AMO),
AMOMAXU_W-> List(Str("amomaxuw"), FMT_AMO),
AMOADD_D-> List(Str("amoaddd "), FMT_AMO),
AMOSWAP_D-> List(Str("amoswapd"), FMT_AMO),
AMOAND_D-> List(Str("amoandd "), FMT_AMO),
AMOOR_D-> List(Str("amoord "), FMT_AMO),
AMOMIN_D-> List(Str("amomind "), FMT_AMO),
AMOMINU_D-> List(Str("amominud"), FMT_AMO),
AMOMAX_D-> List(Str("amomaxd "), FMT_AMO),
AMOMAXU_D-> List(Str("amomaxud"), FMT_AMO),
LR_W-> List(Str("lr.w "), FMT_AMO),
LR_D-> List(Str("lr.d "), FMT_AMO),
SC_W-> List(Str("sc.w "), FMT_AMO),
SC_D-> List(Str("sc.d "), FMT_AMO),
LUI-> List(Str("lui "), FMT_L),
ADDI-> List(Str("addi "), FMT_I),
SLTI -> List(Str("slti "), FMT_I),
SLTIU-> List(Str("sltiu "), FMT_I),
ANDI-> List(Str("andi "), FMT_I),
ORI-> List(Str("ori "), FMT_I),
XORI-> List(Str("xori "), FMT_I),
SLLI-> List(Str("slli "), FMT_I),
SRLI-> List(Str("srli "), FMT_I),
SRAI-> List(Str("srai "), FMT_I),
ADD-> List(Str("add "), FMT_R2),
SUB-> List(Str("sub "), FMT_R2),
SLT-> List(Str("slt "), FMT_R2),
SLTU-> List(Str("sltu "), FMT_R2),
AND-> List(Str("and "), FMT_R2),
OR-> List(Str("or "), FMT_R2),
XOR-> List(Str("xor "), FMT_R2),
SLL-> List(Str("sll "), FMT_R2),
SRL-> List(Str("srl "), FMT_R2),
SRA-> List(Str("sra "), FMT_R2),
ADDIW-> List(Str("addiw "), FMT_I),
SLLIW-> List(Str("slliw "), FMT_I),
SRLIW-> List(Str("srliw "), FMT_I),
SRAIW-> List(Str("sraiw "), FMT_I),
ADDW-> List(Str("addw "), FMT_R2),
SUBW-> List(Str("subw "), FMT_R2),
SLLW-> List(Str("sllw "), FMT_R2),
SRLW-> List(Str("srlw "), FMT_R2),
SRAW-> List(Str("sraw "), FMT_R2),
MUL-> List(Str("mul "), FMT_R2),
MULH-> List(Str("mulh "), FMT_R2),
MULHU-> List(Str("mulhu "), FMT_R2),
MULHSU-> List(Str("mulhsu "), FMT_R2),
MULW-> List(Str("mulw "), FMT_R2),
DIV-> List(Str("div "), FMT_R2),
DIVU-> List(Str("divu "), FMT_R2),
REM-> List(Str("rem "), FMT_R2),
REMU-> List(Str("remu "), FMT_R2),
DIVW-> List(Str("divw "), FMT_R2),
DIVUW-> List(Str("divuw "), FMT_R2),
REMW-> List(Str("remw "), FMT_R2),
REMUW-> List(Str("remuw "), FMT_R2),
SYSCALL-> List(Str("syscall "), FMT_0),
SETPCR-> List(Str("setpcr "), FMT_I),
CLEARPCR-> List(Str("clearpcr"), FMT_I),
ERET-> List(Str("eret "), FMT_0),
FENCE-> List(Str("fence "), FMT_0),
FENCE_I-> List(Str("fence.i "), FMT_0),
MFPCR-> List(Str("mfpcr "), FMT_R2),
MTPCR-> List(Str("mtpcr "), FMT_R2),
RDTIME-> List(Str("rdtime "), FMT_R0),
RDCYCLE-> List(Str("rdcycle "), FMT_R0),
RDINSTRET-> List(Str("rdinstrt"), FMT_R0),
FCVT_S_D-> List(Str("fcvt.sd "), FMT_F1),
FCVT_D_S-> List(Str("fcvt.ds "), FMT_F1),
FSGNJ_S-> List(Str("fsgnj.s "), FMT_F2),
FSGNJ_D-> List(Str("fsgnj.d "), FMT_F2),
FSGNJX_S-> List(Str("fsgnx.s "), FMT_F2),
FSGNJX_D-> List(Str("fsgnx.d "), FMT_F2),
FSGNJN_S-> List(Str("fsgnjn.s"), FMT_F2),
FSGNJN_D-> List(Str("fsgnjn.d"), FMT_F2),
FMIN_S-> List(Str("fmin.s "), FMT_F2),
FMIN_D-> List(Str("fmin.d "), FMT_F2),
FMAX_S-> List(Str("fmax.s "), FMT_F2),
FMAX_D-> List(Str("fmax.d "), FMT_F2),
FADD_S-> List(Str("fadd.s "), FMT_F2),
FADD_D-> List(Str("fadd.d "), FMT_F2),
FSUB_S-> List(Str("fsub.s "), FMT_F2),
FSUB_D-> List(Str("fsub.d "), FMT_F2),
FMUL_S-> List(Str("fmul.s "), FMT_F2),
FMUL_D-> List(Str("fmul.d "), FMT_F2),
FMADD_S-> List(Str("fmadd.s "), FMT_F3),
FMADD_D-> List(Str("fmadd.d "), FMT_F3),
FMSUB_S-> List(Str("fmsub.s "), FMT_F3),
FMSUB_D-> List(Str("fmsub.d "), FMT_F3),
FNMADD_S-> List(Str("fnmadd.s"), FMT_F3),
FNMADD_D-> List(Str("fnmadd.d"), FMT_F3),
FNMSUB_S-> List(Str("fnmsub.s"), FMT_F3),
FNMSUB_D-> List(Str("fnmsub.d"), FMT_F3),
FMV_X_S-> List(Str("fmv.x.s "), FMT_XF1),
FMV_X_D-> List(Str("fmv.x.d "), FMT_XF1),
FCVT_W_S-> List(Str("fcvt.ws "), FMT_XF1),
FCVT_W_D-> List(Str("fcvt.wd "), FMT_XF1),
FCVT_WU_S-> List(Str("fcvt.wus"), FMT_XF1),
FCVT_WU_D-> List(Str("fcvt.wud"), FMT_XF1),
FCVT_L_S-> List(Str("fcvt.ls "), FMT_XF1),
FCVT_L_D-> List(Str("fcvt.ld "), FMT_XF1),
FCVT_LU_S-> List(Str("fcvt.lus"), FMT_XF1),
FCVT_LU_D-> List(Str("fcvt.lud"), FMT_XF1),
FEQ_S-> List(Str("feq.s "), FMT_XF2),
FEQ_D-> List(Str("feq.d "), FMT_XF2),
FLT_S-> List(Str("flt.s "), FMT_XF2),
FLT_D-> List(Str("flt.d "), FMT_XF2),
FLE_S-> List(Str("fle.s "), FMT_XF2),
FLE_D-> List(Str("fle.d "), FMT_XF2),
FMV_S_X-> List(Str("fmv.s.x "), FMT_FX),
FMV_D_X-> List(Str("fmv.d.x "), FMT_FX),
FCVT_S_W-> List(Str("fcvt.sw "), FMT_FX),
FCVT_D_W-> List(Str("fcvt.dw "), FMT_FX),
FCVT_S_WU-> List(Str("fcvt.swu"), FMT_FX),
FCVT_D_WU-> List(Str("fcvt.dwu"), FMT_FX),
FCVT_S_L-> List(Str("fcvt.sl "), FMT_FX),
FCVT_D_L-> List(Str("fcvt.dl "), FMT_FX),
FCVT_S_LU-> List(Str("fcvt.slu"), FMT_FX),
FCVT_D_LU-> List(Str("fcvt.dlu"), FMT_FX),
FRSR-> List(Str("frsr "), FMT_R0),
FSSR-> List(Str("fssr "), FMT_R1),
FLW-> List(Str("flw "), FMT_FLD),
FLD-> List(Str("fld "), FMT_FLD),
FSW-> List(Str("fsw "), FMT_FST),
FSD-> List(Str("fsd "), FMT_FST)
)
}