Add early out to multiplier
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@ -54,11 +54,14 @@ class MulDiv(mulUnroll: Int = 1, earlyOut: Boolean = false)(implicit conf: Rocke
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val accum = mulReg(2*mulw,mulw).toSInt
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val mpcand = divisor.toSInt
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val prod = mplier(mulUnroll-1,0) * mpcand + accum
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val nextMulReg = Cat(prod, mplier(mulw-1,mulUnroll)).toUInt
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val eOut = Bool(earlyOut) && count > 0 &&
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(0 until mulw/mulUnroll).map(i => i > mulw/mulUnroll-1-count || mplier((i+1)*mulUnroll-1,i*mulUnroll) === 0).reduce(_&&_)
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val eOutValue = mulReg >> (mulw/mulUnroll-count)(log2Up(mulw/mulUnroll)-1,0)*mulUnroll
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val nextMulReg = Mux(eOut, eOutValue, Cat(prod, mplier(mulw-1,mulUnroll)))
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remainder := Cat(nextMulReg >> w, Bool(false), nextMulReg(w-1,0)).toSInt
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count := count + 1
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when (count === mulw/mulUnroll-1) {
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when (count === mulw/mulUnroll-1 || eOut) {
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state := s_done
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when (AVec(FN_MULH, FN_MULHU, FN_MULHSU) contains req.fn) {
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state := s_move_rem
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