Andrew Waterman
5b7f3c3006
Don't use clone
2015-07-15 17:30:50 -07:00
Andrew Waterman
be2ff6dec7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:33:46 -07:00
Andrew Waterman
a78e28523c
Chisel3: Don't mix Mux types
2015-07-11 14:06:08 -07:00
Andrew Waterman
3233867390
Use Chisel3 SeqMem construct
2015-07-11 13:34:57 -07:00
Henry Cook
5ed2899e56
Merge pull request #10 from wsong83/fix
...
L1 D$ writeback unit, reduce re-read data array
2015-07-06 15:18:49 -07:00
Andrew Waterman
5362e2bbbd
New machine-mode timer facility
2015-07-05 16:38:49 -07:00
Andrew Waterman
5e009ecc75
Fix an apparently benign PC sign-extension bug
2015-06-11 16:08:39 -07:00
Wei Song
4db60d9e9d
code clean in dcache, no need to check the condition twice.
2015-06-02 22:06:12 +01:00
Wei Song
b6e68773fd
nbdcache, writeback unit: when release is not ready and data is not ready for a beat too, no need to re-read data array.
2015-05-30 16:25:27 +01:00
Andrew Waterman
6a9390c50e
Avoid spurious D$ assertion failures
...
For the Rocket pipeline, this fix is needless and the problem is that the
assertion is too conservative, but I solved it this way to avoid problems
for other plausible use cases where physical and virtual accesses are
intermixed.
2015-05-19 03:00:53 -07:00
Andrew Waterman
f460cb6c54
Update to privileged architecture 1.7
2015-05-19 02:32:21 -07:00
Andrew Waterman
254498042a
Fix Split for 0-width wires
2015-05-18 18:23:17 -07:00
Andrew Waterman
d31b26c342
Clean up handling of icache's io.cpu.npc signal
2015-05-18 18:22:48 -07:00
Christopher Celio
b09832f1b5
ICache now returns the "next PC" signal.
...
useful for other modules that need access to the fetch PC on the
cycle it is sent to the SRAM.
2015-05-07 04:53:05 -07:00
Henry Cook
a315fe93c1
simplify ClientMetadata.makeRelease
2015-04-20 10:46:24 -07:00
Henry Cook
3048f4785a
HeaderlessTileLinkIO -> ClientTileLinkIO
2015-04-17 16:56:53 -07:00
Henry Cook
49f1c0aa7b
moved ecc lib to uncore
2015-04-13 15:58:10 -07:00
Henry Cook
91e882e3f8
Use HeaderlessTileLinkIO
2015-04-13 15:58:10 -07:00
Christopher Celio
517d0d4b89
feedback on PR
2015-04-12 18:44:03 -07:00
Christopher Celio
4d6ebded02
Added assert to nbdcache
2015-04-11 02:58:34 -07:00
Christopher Celio
a564f08702
Rename dmem.sret signal to more accurate invalidate_lr
2015-04-11 02:26:33 -07:00
Christopher Celio
8fc2d38ca9
Removed unnecessary signal in CSRIO
2015-04-11 02:20:34 -07:00
Christopher Celio
2f88c5ca9d
Renamed PCR to CSR
2015-04-11 02:16:44 -07:00
Christopher Celio
11dbd4221a
Fixed front-end to support four-wide fetch.
2015-04-10 17:53:47 -07:00
Andrew Waterman
9ade0e41cc
Integrate divide/sqrt unit
2015-04-04 16:39:17 -07:00
Andrew Waterman
fe27b9b1b2
Support writing sstatus.fs even without an FPU
2015-04-04 15:20:18 -07:00
Andrew Waterman
bce62d5774
Update PTE format to reflect reserved bits
2015-04-04 15:19:15 -07:00
Andrew Waterman
d912ea265e
New virtual memory implementation (Sv39)
2015-03-27 16:20:59 -07:00
Andrew Waterman
faada5f110
Mask off LSBs of sepc/mepc/stvec
...
Therefore, they cannot generate misaligned instruction exceptions.
When a misaligned instruction exception does occur, mbadaddr
retains the misaligned PC bits, so no information is actually lost.
2015-03-25 00:20:58 -07:00
Andrew Waterman
543ac91cf2
Misaligned fetches can't happen at the I$ anymore
...
They are caught before the I$ ever sees them, so leverage that fact.
2015-03-24 23:55:43 -07:00
Andrew Waterman
90b31586ff
Misc. CSR fixes/improvements
...
- Support RV32 mstatus register
- Don't ignore mstatus.stie bit
- Support custom M-mode R/W CSRs for Raven chip
2015-03-24 23:50:18 -07:00
Andrew Waterman
822698b567
support disabling supervisor mode (via UseVM parameter)
2015-03-24 19:32:45 -07:00
Andrew Waterman
0332c1e7fe
Reduce latency of page table walks
...
A small cache in the PTW caches non-leaf PTEs, reducing latency and D$ misses.
2015-03-24 18:58:38 -07:00
Andrew Waterman
31d17cbf86
Hard-wire LSB of JALR to 0, as sent to BTB
2015-03-21 00:16:34 -07:00
Yunsup Lee
53617d6df5
fix long-standing dcache bug
...
have to initialize register, if it is used the same cycle it is begin written
2015-03-17 21:45:17 -07:00
Yunsup Lee
5b4653b621
fix rocc exception/s bit
2015-03-17 05:08:23 -07:00
Andrew Waterman
66388be1ce
Merge [shm]call into ecall, [shm]ret into eret
2015-03-17 02:24:41 -07:00
Andrew Waterman
2c875555a2
Separate exception return control from exception control
2015-03-17 00:14:32 -07:00
Andrew Waterman
e85c54cc4b
New privileged ISA implementation
2015-03-14 02:49:07 -07:00
Yunsup Lee
ebbd14254c
uncached port should be a HeaderlessUncachedTileLinkIO type
2015-03-13 02:12:23 -07:00
Henry Cook
51e4cd7616
Added UncachedTileLinkIO port to RocketTile, simplify arbitration
2015-03-12 16:30:04 -07:00
Yunsup Lee
ea018b3d84
stall rocket decode when not rocc ready
2015-03-11 22:33:03 -07:00
Colin Schmidt
e293d89035
fix decodelogic bug for bitwidths >= 64 s/1L/BigInt(1)/
2015-03-10 10:28:05 -07:00
Henry Cook
95aa295c39
Use HeaderlessTileLinkIO to cut down on unconnected port errors in VCS
2015-03-09 16:34:43 -07:00
Henry Cook
b36d751250
sret bugfix: bypass arbiter
2015-03-05 13:14:16 -08:00
Christopher Celio
06dea3790a
Removed sret from ptw; sret now comes thru io.cpu to dcache
2015-03-03 16:50:41 -08:00
Christopher Celio
5d07733057
Removed TLBPTWIO from the io.cpu bundle for icache/dcache
2015-03-03 16:40:39 -08:00
Henry Cook
1e0c16c557
new metadata api
2015-02-28 17:00:32 -08:00
Henry Cook
0b131173e6
WritebackUnit multibeat control logic bugfix
2015-02-16 10:59:57 -08:00
Henry Cook
aa46b8b72d
Slightly refactor TLBResp
2015-02-03 19:32:37 -08:00
Stephen Twigg
3d35ccd401
Explicitely convert results of Bits Muxes to UInt
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Chisel updated to emit SInt result instead of UInt so this commit addresses this change.
2015-02-03 18:10:54 -08:00
Henry Cook
741e6b77ad
Rename some params, use refactored TileLink
2015-02-01 20:37:31 -08:00
Scott Beamer
00e074cdd9
fixes slight bug for non-power of 2 number of ras entries
2015-01-29 15:29:25 -08:00
Andrew Waterman
a98127c09e
Merge branch 'ss-frontend'
2015-01-04 20:26:38 -08:00
Andrew Waterman
b70f7683d3
Merge branch 'master' into ss-frontend
...
Conflicts:
src/main/scala/ctrl.scala
2015-01-04 19:59:18 -08:00
Andrew Waterman
87ad1a5703
More control cleanup
2015-01-04 19:46:01 -08:00
Andrew Waterman
2aee85cb11
Flush pipeline from MEM stage
...
This means we no longer have to rely on the instruction behind a serializing
instruction being valid, simplifying the control. But we have to be a
little more cautious when flusing the I$/ITLB/BTB.
2015-01-04 16:40:16 -08:00
Andrew Waterman
94b75c7cb1
Continue refactoring control
2015-01-04 15:32:05 -08:00
Andrew Waterman
6181de4cc9
Much refactor, so control
2015-01-03 13:34:38 -08:00
Henry Cook
1cb65d5ec1
%s/master/manager/g
2014-12-29 22:56:18 -08:00
Henry Cook
77e5e6b561
refill bug
2014-12-17 19:29:28 -08:00
Henry Cook
08dcf4c6ca
refactor cache params
2014-12-17 14:28:05 -08:00
Henry Cook
d29793d1f7
cleanup CoherenceMetadata and coherence params
2014-12-15 19:23:38 -08:00
Henry Cook
c9320862ae
add l2 dmem signal to rocc
2014-12-12 16:55:08 -08:00
Henry Cook
72ea24283b
multibeat TL; passes all tests
2014-12-12 16:54:33 -08:00
Christopher Celio
f19b3ca43e
Deleted extra spaces at EOL in ctrl.scala
2014-11-16 22:04:33 -08:00
Christopher Celio
6749f67b7f
Fixed BHT update error.
...
- separated out BTB/BHT update
- BHT updates counters on every branch
- BTB update only on mispredicted and taken branches
2014-11-16 22:02:27 -08:00
Henry Cook
b7b2923bff
Cleanup MSHR internal bundles
2014-11-11 18:18:35 -08:00
Henry Cook
c9e7874818
Major tilelink revision for uncached message types
2014-11-11 17:36:48 -08:00
Christopher Celio
fea31d2167
Significant changes and fixes to BTB for superscalar fetch.
...
- BTBUpdate only occurs on mispredicts now.
- RASUpdate broken out from BTBUpdate (allows RASUpdate to be performed in
Decode).
- Added optional 2nd CAM port to BTB for updates (for when updates to the
BTB may occur out-of-order).
- Fixed resp.mask bit logic.
2014-11-11 03:34:05 -08:00
Henry Cook
bf901e4bca
Remove master_xact_id from Release
2014-11-06 12:09:45 -08:00
Christopher Celio
3be3cd7731
Fixed error with icache/btb resp mask.
2014-11-03 01:13:22 -08:00
Christopher Celio
08d2c13330
Fixed btb/icache bugs regarding resp mask, fw==1
2014-10-20 18:45:23 -07:00
Christopher Celio
91efdc379b
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Also fixed bridx logic and zero-width wire logic.
Conflicts:
src/main/scala/btb.scala
2014-10-14 18:10:29 -07:00
Andrew Waterman
7bb7299018
Don't pollute BTB with PC+4 target predictions
2014-10-14 17:28:37 -07:00
Christopher Celio
59eb7d194d
Finalize superscalar btb.
2014-10-03 16:08:08 -07:00
Andrew Waterman
cde7c9d869
simplify CSR decoding code
2014-10-03 14:31:26 -07:00
Christopher Celio
99614e37aa
Merge remote-tracking branch 'origin/master' into ss-frontend
...
Conflicts:
src/main/scala/btb.scala
src/main/scala/core.scala
2014-10-03 04:22:58 -07:00
Christopher Celio
9cc35dee9a
Returned history update to fetch.
...
- Global history only contains branches.
- Only update BHT and history on BTB hits.
- Gate off speculative update on stall or icmiss.
- Fixed bug where BHT updates were delayed a cycle.
2014-09-29 21:41:07 -07:00
Christopher Celio
8ccd07cfeb
Moved updating global history from fetch to decode.
...
- No longer update global history in fetch stage.
- Only update global history when instruction is a branch.
- Does allow for the possibility of back-to-back branches to see
slightly different histories on subsequent executions.
2014-09-28 05:16:36 -07:00
Christopher Celio
681b43f398
Bug fixes with global history register.
...
- Updated in fetch speculatively.
* Updates gated off by cpu.resp.fire().
* BTB direction factored into history update.
- All branches update the BHT.
- Each instruction carries history; index into BHT is recomputed by
passing in mem_reg_pc.
2014-09-26 10:39:57 -07:00
Christopher Celio
a71bdbbc54
Update history register in fetch speculatively
2014-09-26 05:42:08 -07:00
Christopher Celio
f917810061
Removed RocketCoreParameters from use.
...
- The nbdache (among others?) use CoreParameters, which has nothing to do with RetireWidth requirements.
- This conflicts with other cores which uses nbdcache.
- RocketCoreParameters may be unneccessary, and the require() check can be moved deeper into Rocket.
2014-09-26 05:14:50 -07:00
Christopher Celio
868e747656
Factored out Rocket specifics from CoreParameters
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- Added new RocketCoreParameters
- Other cores using Rocket as a library will no longer conflict against
Rocket's requires().
2014-09-25 18:52:58 -07:00
Henry Cook
8eb64205f5
bug fix for nbdcache s2_data
2014-09-25 12:00:20 -07:00
Henry Cook
b55c38cdc7
Remove spurious vec consts
2014-09-25 12:00:20 -07:00
Adam Izraelevitz
3e256439c9
Add abstract class Tile
2014-09-24 13:04:20 -07:00
Christopher Celio
180d3d365d
Expanded front-end to support superscalar fetch.
2014-09-17 14:24:03 -07:00
Yunsup Lee
238f7761f6
update README
2014-09-17 11:23:25 -07:00
Yunsup Lee
8abf62fae3
add LICENSE
2014-09-12 18:06:41 -07:00
Yunsup Lee
25180b71f7
add LICENSE
2014-09-12 15:36:42 -07:00
Andrew Waterman
a999c055ed
Don't take an interrupt when EX stage PC is invalid
...
It was possible to take an interrupt on the instruction in the shadow of
a short forward branch. EPC would thus get the wrong value, and so
a wrong-path instruction would be executed upon return from interrupt.
h/t Yunsup
2014-09-11 01:46:52 -07:00
Henry Cook
5eb5e9eaf5
Standardize ()=>Module(...) top-level Parameters
2014-09-07 17:54:41 -07:00
Henry Cook
5e2f98747f
Merge branch 'dse'
2014-09-06 06:10:15 -07:00
Scott Beamer
600c5d50a9
better fix with explanation of sbt issue
2014-09-02 15:14:56 -07:00
Scott Beamer
f9922a106b
fixes sbt error during first run
2014-09-02 14:34:36 -07:00
Henry Cook
b42a2ab40a
Final parameter refactor
2014-09-01 13:28:58 -07:00
Adam Izraelevitz
2d6aafc32e
Merge branch 'dse' of github.com:ucb-bar/rocket-staging into HEAD
2014-09-01 11:23:50 -07:00
Sagar Karandikar
83c6c2c9e2
rename refs to zynq-fpga to fpga-zynq
2014-08-29 10:26:48 -07:00
Henry Cook
6a4193cf90
minor cache param cleanup
2014-08-19 11:38:46 -07:00