riscv/rocket-chip
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Removed unnecessary signal in CSRIO

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Christopher Celio 2015-04-11 02:20:34 -07:00
parent 2f88c5ca9d
commit 8fc2d38ca9
1 changed files with 0 additions and 1 deletions
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rocket/src/main/scala/csr.scala
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@ -93,7 +93,6 @@ class CSRFileIO extends CoreBundle {
val uarch_counters = Vec.fill(16)(UInt(INPUT, log2Up(1+retireWidth)))
val custom_mrw_csrs = Vec.fill(params(NCustomMRWCSRs))(UInt(INPUT, xLen))
val cause = UInt(INPUT, xLen)
val mbadaddr_wen = Bool(INPUT)
val pc = SInt(INPUT, vaddrBits+1)
val fatc = Bool(OUTPUT)
val time = UInt(OUTPUT, xLen)