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Rename dmem.sret signal to more accurate invalidate_lr

This commit is contained in:
Christopher Celio 2015-04-11 02:26:33 -07:00
parent 8fc2d38ca9
commit a564f08702
4 changed files with 5 additions and 5 deletions

View File

@ -674,7 +674,7 @@ class Control extends CoreModule
io.dmem.req.bits.cmd := ex_ctrl.mem_cmd
io.dmem.req.bits.typ := ex_ctrl.mem_type
io.dmem.req.bits.phys := Bool(false)
io.dmem.sret := wb_xcpt // obviously not an sret, but sufficient
io.dmem.invalidate_lr := wb_xcpt
io.rocc.cmd.valid := wb_rocc_val
io.rocc.exception := wb_xcpt && io.dpath.status.xs.orR

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@ -83,7 +83,7 @@ class HellaCacheIO extends CoreBundle {
val resp = Valid(new HellaCacheResp).flip
val replay_next = Valid(Bits(width = coreDCacheReqTagBits)).flip
val xcpt = (new HellaCacheExceptions).asInput
val sret = Bool(OUTPUT)
val invalidate_lr = Bool(OUTPUT)
val ordered = Bool(INPUT)
}
@ -752,7 +752,7 @@ class HellaCache extends L1HellaCacheModule {
lrsc_count := 0
}
}
when (io.cpu.sret) { lrsc_count := 0 }
when (io.cpu.invalidate_lr) { lrsc_count := 0 }
val s2_data = Vec.fill(nWays){Bits(width = encRowBits)}
for (w <- 0 until nWays) {

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@ -123,7 +123,7 @@ class AccumulatorExample extends RoCC
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores...
io.mem.sret := false
io.mem.invalidate_lr := false
io.imem.acquire.valid := false
io.imem.grant.ready := false

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@ -25,7 +25,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val ptw = Module(new PTW(params(NPTWPorts)))
val core = Module(new Core, { case CoreName => "Rocket" })
dcache.io.cpu.sret := core.io.dmem.sret // Bypass sret to dcache
dcache.io.cpu.invalidate_lr := core.io.dmem.invalidate_lr // Bypass signal to dcache
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem